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Searched full:fclk (Results 1 – 25 of 162) sorted by relevance

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/openbmc/linux/drivers/usb/host/
H A Dehci-sh.c13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 ret = clk_enable(priv->fclk); in ehci_hcd_sh_probe()
144 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
162 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
H A Dohci-at91.c54 struct clk *fclk; member
78 clk_set_rate(ohci_at91->fclk, 48000000); in at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); in at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); in at91_stop_clock()
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); in usb_hcd_at91_probe()
216 if (IS_ERR(ohci_at91->fclk)) { in usb_hcd_at91_probe()
218 retval = PTR_ERR(ohci_at91->fclk); in usb_hcd_at91_probe()
/openbmc/qemu/hw/char/
H A Domap_uart.c31 omap_clk fclk; member
51 qemu_irq irq, omap_clk fclk, omap_clk iclk, in omap_uart_init() argument
58 s->fclk = fclk; in omap_uart_init()
61 omap_clk_getrate(fclk) / 16, in omap_uart_init()
/openbmc/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap4-dss.txt14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
H A Dti,omap3-dss.txt14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
H A Dti,omap5-dss.txt14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
H A Dti,dra7-dss.txt14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
/openbmc/linux/drivers/media/dvb-frontends/
H A Ds5h1420.c39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
501 * divide fclk by 1000000 to get the correct value. */ in s5h1420_setfreqoffset()
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
529 * divide fclk by 1000000 to get the correct value. */ in s5h1420_getfreqoffset()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
666 /* set s5h1420 fclk PLL according to desired symbol rate */ in s5h1420_set_frontend()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
[all …]
H A Dcx24110.c50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
245 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
H A Dmb86a20s.h16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member
/openbmc/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_1_ppsmc.h64 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
68 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
74 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
79 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
H A Dsmu_v13_0_4_ppsmc.h73 #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
92 #define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
/openbmc/linux/drivers/iio/adc/
H A Dad7124.c266 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
268 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
270 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
272 * fCLK is the master clock frequency in ad7124_set_channel_odr()
276 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
285 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
286 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
888 unsigned int fclk, power_mode; in ad7124_setup() local
891 fclk = clk_get_rate(st->mclk); in ad7124_setup()
892 if (!fclk) in ad7124_setup()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c449 /* We will not select WM based on fclk, so leave it as unconstrained */ in dcn314_build_watermark_ranges()
576 /* Find highest valid fclk pstate */ in dcn314_clk_mgr_helper_populate_bw_params()
578 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
579 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()
580 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
585 /* We expect the table to contain at least one valid fclk entry. */ in dcn314_clk_mgr_helper_populate_bw_params()
600 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
604 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && in dcn314_clk_mgr_helper_populate_bw_params()
605 clock_table->DfPstateTable[j].FClk < min_fclk && in dcn314_clk_mgr_helper_populate_bw_params()
607 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c26 struct clk *fclk, phy_clk; member
224 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
225 if (IS_ERR(port->fclk)) { in pcie_clk_init()
226 ret = PTR_ERR(port->fclk); in pcie_clk_init()
230 clk_enable(port->fclk); in pcie_clk_init()
250 clk_disable(port->fclk); in pcie_clk_init()
251 clk_put(port->fclk); in pcie_clk_init()
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-clk-ccf.dtsi13 compatible = "xlnx,fclk";
19 compatible = "xlnx,fclk";
25 compatible = "xlnx,fclk";
31 compatible = "xlnx,fclk";
/openbmc/linux/drivers/clocksource/
H A Dtimer-ti-dm.c122 struct clk *fclk; member
418 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
447 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) in omap_dm_timer_set_source()
457 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
729 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
730 return timer->fclk; in omap_dm_timer_get_fclk()
1136 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1137 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1138 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
1141 ret = devm_clk_notifier_register(dev, timer->fclk, in omap_dm_timer_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dti-omap-hsmmc.txt92 swakeup | | fclk
98 In suspend the fclk is off and the module is dysfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
/openbmc/linux/drivers/pwm/
H A Dpwm-omap-dmtimer.c159 struct clk *fclk; in pwm_omap_dmtimer_config() local
168 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
169 if (!fclk) { in pwm_omap_dmtimer_config()
170 dev_err(chip->dev, "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
176 dev_err(chip->dev, "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c399 /* We will not select WM based on fclk, so leave it as unconstrained */ in vg_build_watermark_ranges()
569 /* Find lowest DPM, FCLK is filled in reverse order*/ in vg_clk_mgr_helper_populate_bw_params()
572 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
587 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
629 { .fclk = 400, .memclk = 400, .voltage = 2800 },
630 { .fclk = 400, .memclk = 400, .voltage = 2800 },
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 }
/openbmc/linux/sound/soc/ti/
H A Domap-dmic.c36 struct clk *fclk; member
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
330 mux = clk_get_parent(dmic->fclk); in omap_dmic_select_fclk()
476 dmic->fclk = devm_clk_get(dmic->dev, "fck"); in asoc_dmic_probe()
477 if (IS_ERR(dmic->fclk)) { in asoc_dmic_probe()
/openbmc/linux/drivers/clk/zynq/
H A Dclkc.c103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, in zynq_clk_register_fclk() argument
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
153 pr_warn("%s: FCLK%u enable failed\n", __func__, in zynq_clk_register_fclk()
154 fclk - fclk0); in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
247 of_property_read_u32(np, "fclk-enable", &fclk_enable); in zynq_clk_setup()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-omap.c297 * bus is busy. It will be changed to 1 on the next IP FCLK clock. in __omap_i2c_init()
355 struct clk *fclk; in omap_i2c_init() local
374 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
375 if (IS_ERR(fclk)) { in omap_i2c_init()
376 error = PTR_ERR(fclk); in omap_i2c_init()
382 fclk_rate = clk_get_rate(fclk); in omap_i2c_init()
383 clk_put(fclk); in omap_i2c_init()
404 * The filter is iclk (fclk for HS) period. in omap_i2c_init()
413 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
414 if (IS_ERR(fclk)) { in omap_i2c_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
28 FCLK will only be enabled if it is actually running at

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