/openbmc/linux/Documentation/devicetree/bindings/soc/tegra/ |
H A D | nvidia,nvec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 26 - description: divider clock 27 - description: fast clock 29 clock-names: 32 - const: div-clk 33 - const: fast-clk [all …]
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/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | nvidia,tegra20-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Thierry Reding <thierry.reding@gmail.com> 9 - Jon Hunter <jonathanh@nvidia.com> 16 - description: Tegra20 has 4 generic I2C controller. This can support 17 master and slave mode of I2C communication. The i2c-tegra driver 19 controller is only compatible with "nvidia,tegra20-i2c". 20 const: nvidia,tegra20-i2c [all …]
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos7885-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source 8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include "exynos-pinctrl.h" 16 etc0: etc0-gpio-bank { 17 gpio-controller; 18 #gpio-cells = <2>; 20 interrupt-controller; 21 #interrupt-cells = <2>; [all …]
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/openbmc/linux/drivers/net/mdio/ |
H A D | mdio-hisi-femac.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Hisilicon Fast Ethernet MDIO Bus Driver 8 #include <linux/clk.h> 24 struct clk *clk; member 32 return readl_poll_timeout(data->membase + MDIO_RWCTRL, in hisi_femac_mdio_wait_ready() 38 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_read() 46 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_read() 52 return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; in hisi_femac_mdio_read() 58 struct hisi_femac_mdio_data *data = bus->priv; in hisi_femac_mdio_write() 67 data->membase + MDIO_RWCTRL); in hisi_femac_mdio_write() [all …]
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/openbmc/linux/drivers/bus/ |
H A D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only 15 #include <linux/clk.h> 41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the 42 * memory continues to drive the data bus after OE is de-asserted. 45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after 49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first 51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first 53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle 55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle 73 * FAST CSn CFG [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/ |
H A D | scg.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 99 /* SCG Fast IRC Control Status Register */ 106 /* SCG Fast IRC Divide Register */ 126 /* SCG Fast IRC Divide Register */ 187 /* 0: Sys-OSC, 1: FIRC */ 286 u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */ 289 u32 firctcfg; /* Fast IRC Trim Configuration Register */ 290 u32 firctriml; /* Fast IRC Trim Low Register */ 292 u32 fircstat; /* Fast IRC Status Register */ 293 u32 firctest; /* Fast IRC Test Register */ [all …]
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/openbmc/u-boot/drivers/clk/at91/ |
H A D | clk-h32mx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #include <clk-uclass.h> 19 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk) in sama5d4_h32mx_clk_get_rate() argument 21 struct pmc_platdata *plat = dev_get_platdata(clk->dev); in sama5d4_h32mx_clk_get_rate() 22 struct at91_pmc *pmc = plat->reg_base; in sama5d4_h32mx_clk_get_rate() 23 ulong rate = gd->arch.mck_rate_hz; in sama5d4_h32mx_clk_get_rate() 25 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) in sama5d4_h32mx_clk_get_rate() 29 dev_dbg(clk->dev, "H32MX clock is too fast\n"); in sama5d4_h32mx_clk_get_rate() 44 { .compatible = "atmel,sama5d4-clk-h32mx" }, 49 .name = "sama5d4-h32mx-clk",
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/openbmc/linux/drivers/i2c/busses/ |
H A D | i2c-stm32f4.c | 1 // SPDX-License-Identifier: GPL-2.0 13 * This driver is based on i2c-st.c 17 #include <linux/clk.h> 31 #include "i2c-stm32.h" 97 * struct stm32f4_i2c_msg - client specific data 98 * @addr: 8-bit slave addr, including r/w bit 113 * struct stm32f4_i2c_dev - private data of the controller 118 * @clk: hw i2c clock 119 * @speed: I2C clock frequency of the controller. Standard or Fast are supported 128 struct clk *clk; member [all …]
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H A D | i2c-designware-core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 188 struct clk; 193 * struct dw_i2c_dev - private i2c-designware data 200 * @clk: input reference clock 225 * @rx_outstanding: current master-rx elements in tx fifo 230 * @fs_hcnt: fast speed HCNT value 231 * @fs_lcnt: fast speed LCNT value 232 * @fp_hcnt: fast plus HCNT value 233 * @fp_lcnt: fast plus LCNT value 239 * -1 if there is no semaphore. [all …]
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H A D | i2c-uniphier-f.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk.h> 82 struct clk *clk; member 99 * TX-FIFO stores slave address in it for the first access. in uniphier_fi2c_fill_txfifo() 103 fifo_space--; in uniphier_fi2c_fill_txfifo() 105 while (priv->len) { in uniphier_fi2c_fill_txfifo() 106 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo() 109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo() 110 priv->len--; in uniphier_fi2c_fill_txfifo() 116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo() [all …]
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H A D | i2c-nomadik.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2009 ST-Ericsson SA 19 #include <linux/clk.h> 25 #define DRIVER_NAME "nmk-i2c" 61 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */ 62 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */ 111 * struct i2c_vendor_data - per-vendor variations 135 * struct i2c_nmk_client - client specific data 136 * @slave_adr: 7-bit slave address 151 * struct nmk_i2c_dev - private data structure of the controller. [all …]
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H A D | i2c-rk3x.c | 1 // SPDX-License-Identifier: GPL-2.0-only 21 #include <linux/clk.h> 83 * struct i2c_spec_values - I2C specification values for various modes 87 * @min_setup_start_ns: min set-up time for a repeated START conditio 89 * @min_data_setup_ns: min data set-up time 90 * @min_setup_stop_ns: min set-up time for STOP condition 139 * struct rk3x_i2c_calced_timings - calculated V1 timings 162 * struct rk3x_i2c_soc_data - SOC-specific data 173 * struct rk3x_i2c - private data of the controller 178 * @clk: function clk for rk3399 or function & Bus clks for others [all …]
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/openbmc/u-boot/drivers/i2c/ |
H A D | aspeed_i2c_global.c | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <clk.h> 27 * APB clk : 100Mhz 30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us 36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us 38 * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us 47 i2c_global->regs = devfdt_get_addr_ptr(dev); in aspeed_i2c_global_probe() 48 if (IS_ERR(i2c_global->regs)) in aspeed_i2c_global_probe() 49 return PTR_ERR(i2c_global->regs); in aspeed_i2c_global_probe() 53 ret = reset_get_by_index(dev, 0, &i2c_global->reset); in aspeed_i2c_global_probe() [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-dw-bt1.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 // Baikal-T1 DW APB SPI and System Boot SPI driver 12 #include <linux/clk.h> 24 #include <linux/spi/spi-mem.h> 27 #include "spi-dw.h" 34 struct clk *clk; member 52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create() 54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create() 55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create() 56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create() [all …]
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/openbmc/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-msm8974pro-sony-xperia-shinano-castor.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "qcom-msm8974pro.dtsi" 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 11 compatible = "sony,xperia-castor", "qcom,msm8974pro", "qcom,msm8974"; 12 chassis-type = "tablet"; 20 stdout-path = "serial0:115200n8"; 23 gpio-keys { 24 compatible = "gpio-keys"; [all …]
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H A D | qcom-msm8974-sony-xperia-rhine.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "qcom-msm8974.dtsi" 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 15 stdout-path = "serial0:115200n8"; 18 gpio-keys { 19 compatible = "gpio-keys"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&gpio_keys_pin_a>; [all …]
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H A D | qcom-msm8974pro-fairphone-fp2.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "qcom-msm8974pro.dtsi" 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 12 chassis-type = "handset"; 21 stdout-path = "serial0:115200n8"; 24 gpio-keys { 25 compatible = "gpio-keys"; 27 pinctrl-names = "default"; [all …]
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/openbmc/linux/drivers/clk/at91/ |
H A D | clk-h32mx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * clk-h32mx.c 7 * Alexandre Belloni <alexandre.belloni@free-electrons.com> 10 #include <linux/clk-provider.h> 12 #include <linux/clk/at91_pmc.h> 34 regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); in clk_sama5d4_h32mx_recalc_rate() 39 pr_warn("H32MX clock is too fast\n"); in clk_sama5d4_h32mx_recalc_rate() 54 if (rate - div < *parent_rate - rate) in clk_sama5d4_h32mx_round_rate() 67 return -EINVAL; in clk_sama5d4_h32mx_set_rate() 72 regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR, in clk_sama5d4_h32mx_set_rate() [all …]
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/openbmc/u-boot/board/keymile/km_arm/ |
H A D | kwbimage_256M8_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 7 # Refer doc/README.kwbimage for more details about how-to configure 10 # This configuration applies to COGE5 design (ARM-part) 11 # Two 8-Bit devices are connected on the 16-Bit bus on the same 12 # chip-select. The supported devices are 13 # MT47H256M8EB-3IT:C 14 # MT47H256M8EB-25EIT:C 20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) 22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) [all …]
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H A D | kwbimage_128M16_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 12 # Refer doc/README.kwbimage for more details about how-to configure 20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) 21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) 22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) 23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) 24 # bit 19-16: 1, MPPSel4 NF_IO[6] 25 # bit 23-20: 1, MPPSel5 NF_IO[7] 26 # bit 27-24: 1, MPPSel6 SYSRST_O 27 # bit 31-28: 0, MPPSel7 GPO[7] [all …]
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
H A D | dram.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 16 #include <asm/arch/clk.h> 21 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; variable 29 writel(1, &emc->ctrl); in ddr_init() 30 writel(0, &emc->config); in ddr_init() 32 writel(0x7FF, &emc->refresh); in ddr_init() 33 /* Determine CLK */ in ddr_init() 36 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init() 37 writel(dram->config0, &emc->config0); in ddr_init() [all …]
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/openbmc/linux/drivers/clocksource/ |
H A D | timer-fttmr010.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * Based on a rewrite of arch/arm/mach-gemini/timer.c: 7 * Copyright (C) 2001-2006 Storlink, Corp. 8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 18 #include <linux/clk.h> 81 * - aspeed timer overflow interrupt is controlled by bits in Control 83 * - aspeed timers always generate interrupt when either one of the 113 * fast and stateless 124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up() 129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down() [all …]
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H A D | timer-pistachio.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Pistachio clocksource based on general-purpose timers 10 #include <linux/clk.h> 80 raw_spin_lock_irqsave(&pcs->lock, flags); in pistachio_clocksource_read_cycles() 81 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0); in pistachio_clocksource_read_cycles() 82 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0); in pistachio_clocksource_read_cycles() 83 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pistachio_clocksource_read_cycles() 99 val = gpt_readl(pcs->base, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode() 105 gpt_writel(pcs->base, val, TIMER_CFG, timeridx); in pistachio_clksrc_set_mode() 114 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx); in pistachio_clksrc_enable() [all …]
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/openbmc/linux/arch/arm/boot/dts/aspeed/ |
H A D | aspeed-ast2600-evb.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 /dts-v1/; 6 #include "aspeed-g6.dtsi" 7 #include <dt-bindings/gpio/aspeed-gpio.h> 11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 26 reserved-memory { 27 #address-cells = <1>; 28 #size-cells = <1>; 34 compatible = "shared-dma-pool"; 41 compatible = "shared-dma-pool"; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | tegra30.dtsi | 1 #include <dt-bindings/clock/tegra30-car.h> 2 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/memory/tegra30-mc.h> 4 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 interrupt-parent = <&lic>; 13 pcie-controller@00003000 { 14 compatible = "nvidia,tegra30-pcie"; 19 reg-names = "pads", "afi", "cs"; 22 interrupt-names = "intr", "msi"; [all …]
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