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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos7-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-exynos7420.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <clk-uclass.h>
13 #include <dt-bindings/clock/exynos7420-clk.h>
14 #include "clk-pll.h"
40 * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
55 * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
67 static ulong exynos7420_topc_get_rate(struct clk *clk) in exynos7420_topc_get_rate() argument
69 struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev); in exynos7420_topc_get_rate()
71 switch (clk->id) { in exynos7420_topc_get_rate()
75 return priv->sclk_bus0_pll_a; in exynos7420_topc_get_rate()
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/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 Exynos7 series of SoCs which transfers the image data from a video memory
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
25 samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
25 reg-names:
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/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Dsamsung,exynos-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
16 - $ref: ufs-common.yaml
21 - samsung,exynos7-ufs
22 - samsung,exynosautov9-ufs
23 - samsung,exynosautov9-ufs-vh
24 - tesla,fsd-ufs
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/openbmc/u-boot/arch/arm/dts/
H A Dexynos7420.dtsi1 // SPDX-License-Identifier: GPL-2.0+
9 /dts-v1/;
11 #include <dt-bindings/clock/exynos7420-clk.h>
16 compatible = "fixed-clock";
17 clock-output-names = "fin_pll";
18 u-boot,dm-pre-reloc;
19 #clock-cells = <0>;
22 clock_topc: clock-controller@10570000 {
23 compatible = "samsung,exynos7-clock-topc";
25 u-boot,dm-pre-reloc;
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/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7 SoC device tree source
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "samsung,exynos7";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
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H A Dexynos7-espresso.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7 Espresso board device tree source
9 /dts-v1/;
10 #include "exynos7.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/samsung,s2mps11.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Samsung Exynos7 Espresso board based on Exynos7";
17 compatible = "samsung,exynos7-espresso", "samsung,exynos7";
26 stdout-path = &serial_2;
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H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
35 arm-a57-pmu {
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H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
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/openbmc/linux/drivers/clk/samsung/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7 obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o
8 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o
9 obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4412-isp.o
10 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5250.o
11 obj-$(CONFIG_EXYNOS_5250_COMMON_CLK) += clk-exynos5-subcmu.o
12 obj-$(CONFIG_EXYNOS_5260_COMMON_CLK) += clk-exynos5260.o
13 obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
14 obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
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H A Dclk-exynos7.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
10 #include "clk.h"
11 #include <dt-bindings/clock/exynos7-clk.h>
207 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
399 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
581 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
626 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
700 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
817 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
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/openbmc/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
18 #include <linux/clk.h>
141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
183 struct clk *clk; /* operating clock */ member
184 struct clk *pclk; /* bus clock */
200 /* Version of HS-I2C Hardware */
205 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
240 .compatible = "samsung,exynos5-hsi2c",
243 .compatible = "samsung,exynos5250-hsi2c",
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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/clk.h>
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
22 /* Variations in Exynos specific dw-mshc controller */
53 .compatible = "samsung,exynos4210-dw-mshc",
56 .compatible = "samsung,exynos4412-dw-mshc",
59 .compatible = "samsung,exynos5250-dw-mshc",
62 .compatible = "samsung,exynos5420-dw-mshc",
65 .compatible = "samsung,exynos5420-dw-mshc-smu",
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dsamsung,spi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
21 - samsung,s3c6410-spi
22 - samsung,s5pv210-spi # for S5PV210 and S5PC110
23 - samsung,exynos4210-spi
24 - samsung,exynos5433-spi
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
26 samsung,pinctrl-wakeup-interrupt.yaml);
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/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-exynos.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-exynos.c - Samsung Exynos DWC3 Specific Glue layer
15 #include <linux/clk.h>
32 struct clk *clks[DWC3_EXYNOS_MAX_CLOCKS];
43 struct device *dev = &pdev->dev; in dwc3_exynos_probe()
44 struct device_node *node = dev->of_node; in dwc3_exynos_probe()
50 return -ENOMEM; in dwc3_exynos_probe()
53 exynos->dev = dev; in dwc3_exynos_probe()
54 exynos->num_clks = driver_data->num_clks; in dwc3_exynos_probe()
55 exynos->clk_names = (const char **)driver_data->clk_names; in dwc3_exynos_probe()
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/openbmc/linux/drivers/thermal/samsung/
H A Dexynos_tmu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
14 #include <linux/clk.h>
25 #include <dt-bindings/thermal/thermal_exynos.h>
106 /* Exynos7 specific registers */
148 * @clk: pointer to the clock structure.
150 * @sclk: pointer to the clock structure for accessing the tmu special clk.
157 * @gain: gain of amplifier in the positive-TC generator block
160 * in the positive-TC generator block
183 struct clk *clk, *clk_sec, *sclk; member
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/openbmc/linux/drivers/phy/samsung/
H A Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
22 #include "phy-samsung-ufs.h"
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
43 writel(cfg->val, (phy)->reg_pma + cfg->off_1); in samsung_ufs_phy_config()
57 ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS), in samsung_ufs_phy_wait_for_lock_acq()
60 dev_err(ufs_phy->dev, in samsung_ufs_phy_wait_for_lock_acq()
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H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
204 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
207 * @clk: phy clock for register access
224 struct clk *clk; member
225 struct clk *pipeclk;
226 struct clk *utmiclk;
227 struct clk *itpclk;
237 struct clk *ref_clk;
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/openbmc/linux/sound/soc/samsung/
H A Di2s.c1 // SPDX-License-Identifier: GPL-2.0
3 // ALSA SoC Audio Layer - Samsung I2S Controller driver
8 #include <dt-bindings/sound/samsung-i2s.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
23 #include <linux/platform_data/asoc-s3c.h>
28 #include "i2s-regs.h"
104 struct clk *clk; member
107 struct clk *op_clk;
125 struct clk *clk_table[3];
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/openbmc/linux/drivers/iio/adc/
H A Dexynos_adc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_adc.c - Support for ADC in EXYNOS SoCs
5 * 8 ~ 10 channel, 10/12-bit ADC
19 #include <linux/clk.h>
34 #include <linux/platform_data/touchscreen-s3c2410.h>
127 struct clk *clk; member
128 struct clk *sclk;
148 * a wait-callback is used to wait for the conversion result,
171 if (info->data->needs_sclk) in exynos_adc_unprepare_clk()
172 clk_unprepare(info->sclk); in exynos_adc_unprepare_clk()
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/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/clk.h>
30 #include "regs-decon7.h"
47 struct clk *pclk;
48 struct clk *aclk;
49 struct clk *eclk;
50 struct clk *vclk;
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank()
88 if (ctx->suspended) in decon_wait_for_vblank()
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