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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
58 What: /sys/bus/coresight/devices/etm<N>/nrseqstate
65 What: /sys/bus/coresight/devices/etm<N>/nr_resource
[all …]
H A Dsysfs-bus-coresight-devices-etm3x1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
[all …]
/openbmc/linux/tools/perf/util/
H A Dcs-etm.c22 #include "cs-etm.h"
23 #include "cs-etm-decoder/cs-etm-decoder.h"
101 struct cs_etm_auxtrace *etm; member
117 static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm);
118 static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm,
129 * encode the etm queue number as the upper 16 bit and the channel as
188 * The result is cached in etm->pid_fmt so this function only needs to be called
215 return etmq->etm->pid_fmt; in cs_etm__get_pid_fmt()
289 static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu) in get_cpu_data() argument
294 for (i = 0; i < etm->num_cpu; i++) { in get_cpu_data()
[all …]
/openbmc/openbmc-test-automation/security/
H A Dtest_bmc_ssh_security.robot40 …# debug2: MACs ctos: umac-64-etm@openssh.com,umac-128-etm@openssh.com,hmac-sha2-256-etm@openssh.co…
41 # hmac-sha2-512-etm@openssh.com,hmac-sha1-etm@openssh.com,
43 …# debug2: MACs stoc: umac-64-etm@openssh.com,umac-128-etm@openssh.com,hmac-sha2-256-etm@openssh.co…
44 # hmac-sha2-512-etm@openssh.com,hmac-sha1-etm@openssh.com,
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Detm.json3 "PublicDescription": "ETM trace unit output 0",
6 "BriefDescription": "ETM trace unit output 0"
9 "PublicDescription": "ETM trace unit output 1",
12 "BriefDescription": "ETM trace unit output 1"
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Detm.json3 "PublicDescription": "ETM trace unit output 0",
6 "BriefDescription": "ETM trace unit output 0"
9 "PublicDescription": "ETM trace unit output 1",
12 "BriefDescription": "ETM trace unit output 1"
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-etm.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
91 Must be present if the system accesses ETM/PTM management registers via
105 phandle to the cpu this ETM is bound to.
114 description: Output connection from the ETM to CoreSight Trace bus.
/openbmc/linux/Documentation/trace/coresight/
H A Dcoresight.rst41 | # ETM # ::::: | # PTM # ::::: ::::: @ |
76 &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell
89 the basic tracing functionality, enabling components such ETM/PTM, funnel,
101 ETM:
157 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
158 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
210 20010000.etf 20040000.funnel 20100000.stm 22040000.etm
211 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu
213 23040000.etm 23140000.etm 23340000.etm
223 e.g, ETM bound to CPU0 is named "etm0"
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi14 etm@ecc40000 {
31 etm@ecd40000 {
48 etm@ece40000 {
65 etm@ecf40000 {
157 etm@ed440000 {
174 etm@ed540000 {
191 etm@ed640000 {
208 etm@ed740000 {
H A Dhi6220-coresight.dtsi216 etm0: etm@f659c000 {
235 etm1: etm@f659d000 {
254 etm2: etm@f659e000 {
273 etm3: etm@f659f000 {
292 etm4: etm@f65dc000 {
311 etm5: etm@f65dd000 {
330 etm6: etm@f65de000 {
349 etm7: etm@f65df000 {
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm.h144 * struct etm_config - configuration information related to an ETM
145 * @mode: controls various modes supported by this ETM/PTM.
209 * struct etm_drvdata - specifics associated to an ETM component
211 * @atclk: optional clock for the core parts of the ETM.
216 * @arch: ETM/PTM version number.
219 * @sticky_enable: true if ETM base configuration has been done.
262 "invalid CP14 access to ETM reg: %#x", off); in etm_writel()
276 "invalid CP14 access to ETM reg: %#x", off); in etm_readl()
H A Dcoresight-etm3x-core.c33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
111 * @drvdata: etm's private data structure.
349 * Possible to have cores with PTM (supports ret stack) and ETM in etm_parse_event_config()
529 * Configure the ETM only if the CPU is online. If it isn't online in etm_enable_sysfs()
551 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); in etm_enable_sysfs()
647 * DYING hotplug callback is serviced by the ETM driver. in etm_disable_sysfs()
653 * Executing etm_disable_hw on the cpu whose ETM is being disabled in etm_disable_sysfs()
668 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); in etm_disable_sysfs()
781 /* Provide power to ETM: ETMPDCR[3] == 1 */ in etm_init_arch_data()
[all …]
H A Dcoresight-etm-perf.c23 #include "coresight-etm-perf.h"
32 * An ETM context for a running event includes the perf aux handle
33 * and aux_data. For ETM, the aux_data (etm_event_data), consists of
42 * the ETM. Thus the event_data for the session must be part of the ETM context
341 * trace path for each CPU in the mask. If we don't find an ETM in etm_setup_aux()
352 * If there is no ETM associated with this CPU clear it from in etm_setup_aux()
375 /* Find the default sink for this ETM */ in etm_setup_aux()
471 * Check if this ETM is allowed to trace, as decided in etm_event_start()
473 * sink from this ETM. We can't do much in this case if in etm_event_start()
475 * now, simply don't record anything on this ETM. in etm_event_start()
[all …]
H A DKconfig95 the ETM version data tracing may also be available.
115 bool "Control implementation defined overflow support in ETM 4.x driver"
119 ETM 4.x tracer module that can't reduce commit rate automatically.
120 This avoids overflow between the ETM tracer module and the cpu core.
211 SMB is responsible for receiving the trace data from Coresight ETM devices
H A Dcoresight-cti-platform.c127 /* Can optionally have an etm node - return if not */ in cti_plat_create_v8_etm_connection()
143 * The EXTOUT type signals from the ETM are connected to a set of input in cti_plat_create_v8_etm_connection()
152 * We look to see if the ETM coresight device associated with this in cti_plat_create_v8_etm_connection()
158 * probing of the ETM will call into the CTI driver API to update the in cti_plat_create_v8_etm_connection()
171 * must have a cpu, can have an ETM.
210 /* Create the v8 ETM associated connection */ in cti_plat_create_v8_connections()
H A DMakefile6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
18 coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
/openbmc/linux/drivers/clk/mxs/
H A Dclk-imx23.c34 #define ETM (CLKCTRL + 0x00e0) macro
86 lcdif, etm, usb, usb_phy, enumerator
134 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); in mx23_clocks_init()
151 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); in mx23_clocks_init()
H A Dclk-imx28.c37 #define ETM (CLKCTRL + 0x0130) macro
140 ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, enumerator
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29); in mx28_clocks_init()
223 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); in mx28_clocks_init()
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9863a.dtsi412 etm@13040000 {
429 etm@13140000 {
446 etm@13240000 {
463 etm@13340000 {
480 etm@13440000 {
497 etm@13540000 {
514 etm@13640000 {
531 etm@13740000 {
H A Dsc9836.dtsi118 etm@10440000 {
134 etm@10540000 {
150 etm@10640000 {
166 etm@10740000 {
H A Dsc9860.dtsi552 etm@11440000 {
569 etm@11540000 {
586 etm@11640000 {
603 etm@11740000 {
620 etm@11840000 {
637 etm@11940000 {
654 etm@11a40000 {
671 etm@11b40000 {
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
135 "PublicDescription": "ETM extout bit 3",
138 "BriefDescription": "ETM extout bit 3"
/openbmc/linux/tools/perf/arch/arm/util/
H A Dpmu.c15 #include "../../../util/cs-etm.h"
22 /* add ETM default config here */ in perf_pmu__get_default_config()
/openbmc/linux/tools/include/linux/
H A Dcoresight-pmu.h26 * arbitrary values for all ETM versions.
39 /* ETMv4 CONFIGR programming bits for the ETM OPTs */
/openbmc/linux/include/linux/
H A Dcoresight-pmu.h26 * arbitrary values for all ETM versions.
39 /* ETMv4 CONFIGR programming bits for the ETM OPTs */

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