1What:		/sys/bus/coresight/devices/etm<N>/enable_source
2Date:		April 2015
3KernelVersion:  4.01
4Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
5Description:	(RW) Enable/disable tracing on this specific trace entiry.
6		Enabling a source implies the source has been configured
7		properly and a sink has been identidifed for it.  The path
8		of coresight components linking the source to the sink is
9		configured and managed automatically by the coresight framework.
10
11What:		/sys/bus/coresight/devices/etm<N>/cpu
12Date:		April 2015
13KernelVersion:	4.01
14Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
15Description:	(Read) The CPU this tracing entity is associated with.
16
17What:		/sys/bus/coresight/devices/etm<N>/nr_pe_cmp
18Date:		April 2015
19KernelVersion:	4.01
20Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
21Description:	(Read) Indicates the number of PE comparator inputs that are
22		available for tracing.
23
24What:		/sys/bus/coresight/devices/etm<N>/nr_addr_cmp
25Date:		April 2015
26KernelVersion:	4.01
27Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
28Description:	(Read) Indicates the number of address comparator pairs that are
29		available for tracing.
30
31What:		/sys/bus/coresight/devices/etm<N>/nr_cntr
32Date:		April 2015
33KernelVersion:	4.01
34Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
35Description:	(Read) Indicates the number of counters that are available for
36		tracing.
37
38What:		/sys/bus/coresight/devices/etm<N>/nr_ext_inp
39Date:		April 2015
40KernelVersion:	4.01
41Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
42Description:	(Read) Indicates how many external inputs are implemented.
43
44What:		/sys/bus/coresight/devices/etm<N>/numcidc
45Date:		April 2015
46KernelVersion:	4.01
47Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
48Description:	(Read) Indicates the number of Context ID comparators that are
49		available for tracing.
50
51What:		/sys/bus/coresight/devices/etm<N>/numvmidc
52Date:		April 2015
53KernelVersion:	4.01
54Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
55Description:	(Read) Indicates the number of VMID comparators that are available
56		for tracing.
57
58What:		/sys/bus/coresight/devices/etm<N>/nrseqstate
59Date:		April 2015
60KernelVersion:	4.01
61Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
62Description:	(Read) Indicates the number of sequencer states that are
63		implemented.
64
65What:		/sys/bus/coresight/devices/etm<N>/nr_resource
66Date:		April 2015
67KernelVersion:	4.01
68Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
69Description:	(Read) Indicates the number of resource selection pairs that are
70		available for tracing.
71
72What:		/sys/bus/coresight/devices/etm<N>/nr_ss_cmp
73Date:		April 2015
74KernelVersion:	4.01
75Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
76Description:	(Read) Indicates the number of single-shot comparator controls that
77		are available for tracing.
78
79What:		/sys/bus/coresight/devices/etm<N>/reset
80Date:		April 2015
81KernelVersion:	4.01
82Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
83Description: 	(Write) Cancels all configuration on a trace unit and set it back
84		to its boot configuration.
85
86What:		/sys/bus/coresight/devices/etm<N>/mode
87Date:		April 2015
88KernelVersion:	4.01
89Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
90Description: 	(RW) Controls various modes supported by this ETM, for example
91		P0 instruction tracing, branch broadcast, cycle counting and
92		context ID tracing.
93
94What:		/sys/bus/coresight/devices/etm<N>/pe
95Date:		April 2015
96KernelVersion:	4.01
97Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
98Description: 	(RW) Controls which PE to trace.
99
100What:		/sys/bus/coresight/devices/etm<N>/event
101Date:		April 2015
102KernelVersion:	4.01
103Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
104Description: 	(RW) Controls the tracing of arbitrary events from bank 0 to 3.
105
106What:		/sys/bus/coresight/devices/etm<N>/event_instren
107Date:		April 2015
108KernelVersion:	4.01
109Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
110Description: 	(RW) Controls the behavior of the events in bank 0 to 3.
111
112What:		/sys/bus/coresight/devices/etm<N>/event_ts
113Date:		April 2015
114KernelVersion:	4.01
115Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
116Description: 	(RW) Controls the insertion of global timestamps in the trace
117		streams.
118
119What:		/sys/bus/coresight/devices/etm<N>/syncfreq
120Date:		April 2015
121KernelVersion:	4.01
122Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
123Description: 	(RW) Controls how often trace synchronization requests occur.
124
125What:		/sys/bus/coresight/devices/etm<N>/cyc_threshold
126Date:		April 2015
127KernelVersion:	4.01
128Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
129Description: 	(RW) Sets the threshold value for cycle counting.
130
131What:		/sys/bus/coresight/devices/etm<N>/bb_ctrl
132Date:		April 2015
133KernelVersion:	4.01
134Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
135Description: 	(RW) Controls which regions in the memory map are enabled to
136		use branch broadcasting.
137
138What:		/sys/bus/coresight/devices/etm<N>/event_vinst
139Date:		April 2015
140KernelVersion:	4.01
141Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
142Description: 	(RW) Controls instruction trace filtering.
143
144What:		/sys/bus/coresight/devices/etm<N>/s_exlevel_vinst
145Date:		April 2015
146KernelVersion:	4.01
147Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
148Description: 	(RW) In Secure state, each bit controls whether instruction
149		tracing is enabled for the corresponding exception level.
150
151What:		/sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst
152Date:		April 2015
153KernelVersion:	4.01
154Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
155Description: 	(RW) In non-secure state, each bit controls whether instruction
156		tracing is enabled for the corresponding exception level.
157
158What:		/sys/bus/coresight/devices/etm<N>/addr_idx
159Date:		April 2015
160KernelVersion:	4.01
161Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
162Description: 	(RW) Select which address comparator or pair (of comparators) to
163		work with.
164
165What:		/sys/bus/coresight/devices/etm<N>/addr_instdatatype
166Date:		April 2015
167KernelVersion:	4.01
168Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
169Description: 	(RW) Controls what type of comparison the trace unit performs.
170
171What:		/sys/bus/coresight/devices/etm<N>/addr_single
172Date:		April 2015
173KernelVersion:	4.01
174Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
175Description: 	(RW) Used to setup single address comparator values.
176
177What:		/sys/bus/coresight/devices/etm<N>/addr_range
178Date:		April 2015
179KernelVersion:	4.01
180Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
181Description: 	(RW) Used to setup address range comparator values.
182
183What:		/sys/bus/coresight/devices/etm<N>/seq_idx
184Date:		April 2015
185KernelVersion:	4.01
186Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
187Description: 	(RW) Select which sequensor.
188
189What:		/sys/bus/coresight/devices/etm<N>/seq_state
190Date:		April 2015
191KernelVersion:	4.01
192Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
193Description: 	(RW) Use this to set, or read, the sequencer state.
194
195What:		/sys/bus/coresight/devices/etm<N>/seq_event
196Date:		April 2015
197KernelVersion:	4.01
198Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
199Description: 	(RW) Moves the sequencer state to a specific state.
200
201What:		/sys/bus/coresight/devices/etm<N>/seq_reset_event
202Date:		April 2015
203KernelVersion:	4.01
204Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
205Description: 	(RW) Moves the sequencer to state 0 when a programmed event
206		occurs.
207
208What:		/sys/bus/coresight/devices/etm<N>/cntr_idx
209Date:		April 2015
210KernelVersion:	4.01
211Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
212Description: 	(RW) Select which counter unit to work with.
213
214What:		/sys/bus/coresight/devices/etm<N>/cntrldvr
215Date:		April 2015
216KernelVersion:	4.01
217Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
218Description: 	(RW) This sets or returns the reload count value of the
219		specific counter.
220
221What:		/sys/bus/coresight/devices/etm<N>/cntr_val
222Date:		April 2015
223KernelVersion:	4.01
224Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
225Description: 	(RW) This sets or returns the current count value of the
226                specific counter.
227
228What:		/sys/bus/coresight/devices/etm<N>/cntr_ctrl
229Date:		April 2015
230KernelVersion:	4.01
231Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
232Description: 	(RW) Controls the operation of the selected counter.
233
234What:		/sys/bus/coresight/devices/etm<N>/res_idx
235Date:		April 2015
236KernelVersion:	4.01
237Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
238Description: 	(RW) Select which resource selection unit to work with.
239
240What:		/sys/bus/coresight/devices/etm<N>/res_ctrl
241Date:		April 2015
242KernelVersion:	4.01
243Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
244Description: 	(RW) Controls the selection of the resources in the trace unit.
245
246What:		/sys/bus/coresight/devices/etm<N>/ctxid_idx
247Date:		April 2015
248KernelVersion:	4.01
249Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
250Description:	(RW) Select which context ID comparator to work with.
251
252What:		/sys/bus/coresight/devices/etm<N>/ctxid_pid
253Date:		April 2015
254KernelVersion:	4.01
255Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
256Description:	(RW) Get/Set the context ID comparator value to trigger on.
257
258What:		/sys/bus/coresight/devices/etm<N>/ctxid_masks
259Date:		April 2015
260KernelVersion:	4.01
261Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
262Description:	(RW) Mask for all 8 context ID comparator value
263		registers (if implemented).
264
265What:		/sys/bus/coresight/devices/etm<N>/vmid_idx
266Date:		April 2015
267KernelVersion:	4.01
268Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
269Description:	(RW) Select which virtual machine ID comparator to work with.
270
271What:		/sys/bus/coresight/devices/etm<N>/vmid_val
272Date:		April 2015
273KernelVersion:	4.01
274Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
275Description:	(RW) Get/Set the virtual machine ID comparator value to
276		trigger on.
277
278What:		/sys/bus/coresight/devices/etm<N>/vmid_masks
279Date:		April 2015
280KernelVersion:	4.01
281Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
282Description:	(RW) Mask for all 8 virtual machine ID comparator value
283		registers (if implemented).
284
285What:		/sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns
286Date:		December 2019
287KernelVersion:	5.5
288Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
289Description:	(RW) Set the Exception Level matching bits for secure and
290		non-secure exception levels.
291
292What:		/sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop
293Date:		December 2019
294KernelVersion:	5.5
295Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
296Description:	(RW) Access the start stop control register for PE input
297		comparators.
298
299What:		/sys/bus/coresight/devices/etm<N>/addr_cmp_view
300Date:		December 2019
301KernelVersion:	5.5
302Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
303Description:	(Read) Print the current settings for the selected address
304		comparator.
305
306What:		/sys/bus/coresight/devices/etm<N>/sshot_idx
307Date:		December 2019
308KernelVersion:	5.5
309Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
310Description:	(RW) Select the single shot control register to access.
311
312What:		/sys/bus/coresight/devices/etm<N>/sshot_ctrl
313Date:		December 2019
314KernelVersion:	5.5
315Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
316Description:	(RW) Access the selected single shot control register.
317
318What:		/sys/bus/coresight/devices/etm<N>/sshot_status
319Date:		December 2019
320KernelVersion:	5.5
321Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
322Description:	(Read) Print the current value of the selected single shot
323		status register.
324
325What:		/sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl
326Date:		December 2019
327KernelVersion:	5.5
328Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
329Description:	(RW) Access the selected single show PE comparator control
330		register.
331
332What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
333Date:		April 2015
334KernelVersion:	4.01
335Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
336Description:	(Read) Print the content of the OS Lock Status Register (0x304).
337		The value it taken directly  from the HW.
338
339What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr
340Date:		April 2015
341KernelVersion:	4.01
342Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
343Description:	(Read) Print the content of the Power Down Control Register
344		(0x310).  The value is taken directly from the HW.
345
346What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr
347Date:		April 2015
348KernelVersion:	4.01
349Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
350Description:	(Read) Print the content of the Power Down Status Register
351		(0x314).  The value is taken directly from the HW.
352
353What:		/sys/bus/coresight/devices/etm<N>/mgmt/trclsr
354Date:		April 2015
355KernelVersion:	4.01
356Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
357Description:	(Read) Print the content of the SW Lock Status Register
358		(0xFB4).  The value is taken directly from the HW.
359
360What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus
361Date:		April 2015
362KernelVersion:	4.01
363Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
364Description:	(Read) Print the content of the Authentication Status Register
365		(0xFB8).  The value is taken directly from the HW.
366
367What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevid
368Date:		April 2015
369KernelVersion:	4.01
370Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
371Description:	(Read) Print the content of the Device ID Register
372		(0xFC8).  The value is taken directly from the HW.
373
374What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch
375Date:		January 2021
376KernelVersion:	5.12
377Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
378Description:	(Read) Print the content of the Device Architecture Register
379		(offset 0xFBC).  The value is taken directly read
380		from the HW.
381
382What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
383Date:		April 2015
384KernelVersion:	4.01
385Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
386Description:	(Read) Print the content of the Device Type Register
387		(0xFCC).  The value is taken directly from the HW.
388
389What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0
390Date:		April 2015
391KernelVersion:	4.01
392Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
393Description:	(Read) Print the content of the Peripheral ID0 Register
394		(0xFE0).  The value is taken directly from the HW.
395
396What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1
397Date:		April 2015
398KernelVersion:	4.01
399Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
400Description:	(Read) Print the content of the Peripheral ID1 Register
401		(0xFE4).  The value is taken directly from the HW.
402
403What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2
404Date:		April 2015
405KernelVersion:	4.01
406Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
407Description:	(Read) Print the content of the Peripheral ID2 Register
408		(0xFE8).  The value is taken directly from the HW.
409
410What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3
411Date:		April 2015
412KernelVersion:	4.01
413Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
414Description:	(Read) Print the content of the Peripheral ID3 Register
415		(0xFEC).  The value is taken directly from the HW.
416
417What:		/sys/bus/coresight/devices/etm<N>/mgmt/trcconfig
418Date:		February 2016
419KernelVersion:	4.07
420Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
421Description:	(Read) Print the content of the trace configuration register
422		(0x010) as currently set by SW.
423
424What:		/sys/bus/coresight/devices/etm<N>/mgmt/trctraceid
425Date:		February 2016
426KernelVersion:	4.07
427Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
428Description:	(Read) Print the content of the trace ID register (0x040).
429
430What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr0
431Date:		April 2015
432KernelVersion:	4.01
433Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
434Description:	(Read) Returns the tracing capabilities of the trace unit (0x1E0).
435		The value is taken directly from the HW.
436
437What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr1
438Date:		April 2015
439KernelVersion:	4.01
440Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
441Description:	(Read) Returns the tracing capabilities of the trace unit (0x1E4).
442		The value is taken directly from the HW.
443
444What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr2
445Date:		April 2015
446KernelVersion:	4.01
447Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
448Description:	(Read) Returns the maximum size of the data value, data address,
449		VMID, context ID and instruction address in the trace unit
450		(0x1E8).  The value is taken directly from the HW.
451
452What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr3
453Date:		April 2015
454KernelVersion:	4.01
455Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
456Description:	(Read) Returns the value associated with various resources
457		available to the trace unit.  See the Trace Macrocell
458		architecture specification for more details (0x1E8).
459		The value is taken directly from the HW.
460
461What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr4
462Date:		April 2015
463KernelVersion:	4.01
464Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
465Description:	(Read) Returns how many resources the trace unit supports (0x1F0).
466		The value is taken directly from the HW.
467
468What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr5
469Date:		April 2015
470KernelVersion:	4.01
471Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
472Description:	(Read) Returns how many resources the trace unit supports (0x1F4).
473		The value is taken directly from the HW.
474
475What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr8
476Date:		April 2015
477KernelVersion:	4.01
478Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
479Description:	(Read) Returns the maximum speculation depth of the instruction
480		trace stream. (0x180).  The value is taken directly from the HW.
481
482What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr9
483Date:		April 2015
484KernelVersion:	4.01
485Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
486Description:	(Read) Returns the number of P0 right-hand keys that the trace unit
487		can use (0x184).  The value is taken directly from the HW.
488
489What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr10
490Date:		April 2015
491KernelVersion:	4.01
492Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
493Description:	(Read) Returns the number of P1 right-hand keys that the trace unit
494		can use (0x188).  The value is taken directly from the HW.
495
496What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr11
497Date:		April 2015
498KernelVersion:	4.01
499Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
500Description:	(Read) Returns the number of special P1 right-hand keys that the
501		trace unit can use (0x18C).  The value is taken directly from
502		the HW.
503
504What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr12
505Date:		April 2015
506KernelVersion:	4.01
507Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
508Description:	(Read) Returns the number of conditional P1 right-hand keys that
509		the trace unit can use (0x190).  The value is taken directly
510		from the HW.
511
512What:		/sys/bus/coresight/devices/etm<N>/trcidr/trcidr13
513Date:		April 2015
514KernelVersion:	4.01
515Contact:	Mathieu Poirier <mathieu.poirier@linaro.org>
516Description:	(Read) Returns the number of special conditional P1 right-hand keys
517		that the trace unit can use (0x194).  The value is taken
518		directly from the HW.
519
520What:		/sys/bus/coresight/devices/etm<N>/ts_source
521Date:		October 2022
522KernelVersion:	6.1
523Contact:	Mathieu Poirier <mathieu.poirier@linaro.org> or Suzuki K Poulose <suzuki.poulose@arm.com>
524Description:	(Read) When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for
525		trace session. Otherwise -1 indicates an unknown time source. Check
526		trcidr0.tssize to see if a global timestamp is available.
527