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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
H A Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
111 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
77 { .compatible = "fsl,mpc8536-esdhc" },
78 { .compatible = "fsl,esdhc" },
[all …]
H A Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
509 .name = "sdhci-esdhc-mcf",
518 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
H A Dsdhci-pltfm.c65 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
68 if (of_device_is_compatible(np, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
69 of_device_is_compatible(np, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
70 of_device_is_compatible(np, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
71 of_device_is_compatible(np, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
H A Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
H A Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
30 #include "sdhci-esdhc.h"
127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
130 * Define this macro DMA error INT for fsl eSDHC
150 * The flag tells that the ESDHC controller is an USDHC block that is
218 * struct esdhc_platform_data - platform data for esdhc on i.MX
366 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
367 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
H A DMakefile79 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o
80 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
86 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
/openbmc/u-boot/doc/
H A DREADME.fsl-esdhc1 Freescale esdhc-specific options
18 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
19 determined by ESDHC IP's endian mode or processor's endian mode.
21 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
22 by ESDHC IP's endian mode or processor's endian mode.
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dmpc8569mds.c329 * Because of an erratum in prototype boards it is impossible to use eSDHC
331 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
349 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); in esdhc_disables_uart0()
364 if (hwconfig("esdhc") && esdhc_disables_uart0()) { in fdt_board_fixup_qe_uart()
365 printf("QE UART: won't enable with esdhc.\n"); in fdt_board_fixup_qe_uart()
405 if (!hwconfig("esdhc")) in board_mmc_init()
408 printf("Enabling eSDHC...\n" in board_mmc_init()
409 " For eSDHC to function, I2C2 "); in board_mmc_init()
428 /* Assign I2C2 signals to eSDHC. */ in board_mmc_init()
434 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */ in board_mmc_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1012a.dtsi56 esdhc0: esdhc@1560000 {
57 compatible = "fsl,esdhc";
64 esdhc1: esdhc@1580000 {
65 compatible = "fsl,esdhc";
H A Dfsl-lx2160a.dtsi119 esdhc0: esdhc@2140000 {
120 compatible = "fsl,esdhc";
131 esdhc1: esdhc@2150000 {
132 compatible = "fsl,esdhc";
H A Dimx53.dtsi66 esdhc1: esdhc@50004000 {
67 compatible = "fsl,imx53-esdhc";
78 esdhc2: esdhc@50008000 {
79 compatible = "fsl,imx53-esdhc";
H A Dfsl-ls1088a.dtsi78 esdhc: esdhc@2140000 { label
79 compatible = "fsl,esdhc";
H A Dfsl-ls2080a.dtsi78 esdhc: esdhc@0 { label
79 compatible = "fsl,esdhc";
/openbmc/qemu/hw/arm/
H A Dfsl-imx25.c71 object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC); in fsl_imx25_init()
242 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 2, in fsl_imx25_realize()
244 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", in fsl_imx25_realize()
246 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", in fsl_imx25_realize()
248 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { in fsl_imx25_realize()
251 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); in fsl_imx25_realize()
252 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, in fsl_imx25_realize()
H A Dfsl-imx6.c84 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC); in fsl_imx6_init()
328 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, in fsl_imx6_realize()
330 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", in fsl_imx6_realize()
332 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", in fsl_imx6_realize()
334 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), errp)) { in fsl_imx6_realize()
337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); in fsl_imx6_realize()
338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, in fsl_imx6_realize()
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
H A Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
H A Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
H A Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
H A Dp1010si-post.dtsi172 /include/ "pq3-esdhc-0.dtsi"
174 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_devdis.h13 { "esdhc", 0x0, 0x20000000 }, /* eSDHC */
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi159 esdhc0: esdhc@1560000 {
160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
178 esdhc1: esdhc@1580000 {
179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";

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