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/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/openbmc/linux/Documentation/devicetree/bindings/power/
H A Ddomain-idle-state.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: domain-idle-states
21 "^(cpu|cluster|domain)-":
29 const: domain-idle-state
31 entry-latency-us:
33 The worst case latency in microseconds required to enter the idle
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H A Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
24 \#power-domain-cells property in the PM domain provider node.
28 pattern: "^(power-controller|power-domain)([@-].*)?$"
30 domain-idle-states:
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/openbmc/linux/kernel/
H A Dlatencytop.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * latencytop.c: Latency display infrastructure
10 * CONFIG_LATENCYTOP enables a kernel latency tracking infrastructure that is
11 * used by the "latencytop" userspace tool. The latency that is tracked is not
12 * the 'traditional' interrupt latency (which is primarily caused by something
13 * else consuming CPU), but instead, it is the latency an application encounters
17 * 1) System level latency
18 * 2) Per process latency
20 * The latency is stored in fixed sized data structures in an accumulated form;
21 * if the "same" latency cause is hit twice, this will be tracked as one entry
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H A DKconfig.preempt1 # SPDX-License-Identifier: GPL-2.0-only
37 This option reduces the latency of the kernel by adding more
40 latency of rescheduling, providing faster application reactions,
52 bool "Preemptible Kernel (Low-Latency Desktop)"
56 This option reduces the latency of the kernel by making
67 embedded system with latency requirements in the milliseconds
71 bool "Fully Preemptible Kernel (Real-Time)"
75 This option turns the kernel into a real-time kernel by replacing
77 preemptible priority-inheritance aware variants, enforcing
79 non-preemptible sections. This makes the kernel, except for very
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/openbmc/linux/kernel/trace/
H A Dtrace_hwlat.c1 // SPDX-License-Identifier: GPL-2.0
3 * trace_hwlat.c - A simple Hardware Latency detector.
20 * Although certain hardware-inducing latencies are necessary (for example,
22 * and remote management) they can wreak havoc upon any OS-level performance
23 * guarantees toward low-latency, especially when the OS is not even made
27 * sampling the built-in CPU timer, looking for discontiguous readings.
31 * environment requiring any kind of low-latency performance
34 * Copyright (C) 2008-2009 Jon Masters, Red Hat, Inc. <jcm@redhat.com>
35 * Copyright (C) 2013-2016 Steven Rostedt, Red Hat, Inc. <srostedt@redhat.com>
67 static char *thread_mode_str[] = { "none", "round-robin", "per-cpu" };
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 API, which will be used by other function-entry hooking
27 See Documentation/trace/ftrace-design.rst
32 See Documentation/trace/ftrace-design.rst
40 See Documentation/trace/ftrace-design.rst
69 See Documentation/trace/ftrace-design.rst
74 See Documentation/trace/ftrace-design.rst
79 Arch supports the gcc options -pg with -mfentry
84 Arch supports the gcc options -pg with -mrecord-mcount and -nop-mcount
89 Arch supports objtool --mcount
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/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8-ca53.dtsi17 #address-cells = <2>;
18 #size-cells = <0>;
20 idle-states {
21 entry-method = "psci";
23 CPU_SLEEP: cpu-sleep {
24 compatible = "arm,idle-state";
25 local-timer-stop;
26 arm,psci-suspend-param = <0x0000000>;
27 entry-latency-us = <700>;
28 exit-latency-us = <250>;
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/openbmc/linux/drivers/cpuidle/
H A Ddt_idle_states.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "DT idle-states: " fmt
32 idle_state->enter = match_id->data; in init_state_node()
38 idle_state->enter_s2idle = match_id->data; in init_state_node()
40 err = of_property_read_u32(state_node, "wakeup-latency-us", in init_state_node()
41 &idle_state->exit_latency); in init_state_node()
45 err = of_property_read_u32(state_node, "entry-latency-us", in init_state_node()
48 pr_debug(" * %pOF missing entry-latency-us property\n", in init_state_node()
50 return -EINVAL; in init_state_node()
53 err = of_property_read_u32(state_node, "exit-latency-us", in init_state_node()
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/openbmc/linux/arch/alpha/lib/
H A Dev6-stxncpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxncpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@api-networks.com>
6 * Copy no more than COUNT bytes of the null-terminated string from
29 * Furthermore, v0, a3-a5, t11, and $at are untouched.
34 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
36 * E - either cluster
37 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
38 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
50 doesn't like putting the entry point for a procedure somewhere in the
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H A Dev6-stxcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-stxcpy.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
6 * Copy a null-terminated string from SRC to DST.
21 * Furthermore, v0, a3-a5, t11, and t12 are untouched.
26 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
28 * E - either cluster
29 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
30 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
42 doesn't like putting the entry point for a procedure somewhere in the
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt2 ----------------------------------------------
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - cpu_g: Clock mux for the fast CPU cluster.
12 - pll_x: Fast PLL clocksource.
13 - pll_p: Auxiliary PLL used during fast PLL rate changes.
14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
17 - clock-latency: Specify the possible maximum transition latency for clock,
21 --------
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/openbmc/qemu/include/hw/cxl/
H A Dcxl_cdat.h7 * See the COPYING file in the top-level directory.
21 /* Table Access DOE - CXL r3.1 8.1.11 */
25 /* Read Entry - CXL r3.1 8.1.11.1 */
29 /* Read Entry Request - CXL r3.1 8.1.11.1 Table 8-13 */
38 /* Read Entry Response - CXL r3.1 8.1.11.1 Table 8-14 */
47 /* CDAT Table Format - CDAT Table 1 */
57 /* CDAT Structure Types - CDAT Table 2 */
73 /* Device Scoped Memory Affinity Structure - CDAT Table 3 */
88 /* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */
97 uint16_t entry[3]; member
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dpsci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
40 - description:
44 - description:
52 - const: arm,psci-0.2
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&intc>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 xo_board: xo-board {
19 compatible = "fixed-clock";
20 clock-frequency = <76800000>;
21 #clock-cells = <0>;
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H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
19 interrupt-parent = <&intc>;
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/openbmc/linux/kernel/power/
H A Dqos.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * or through a built-in notification mechanism.
18 * global CPU latency QoS requests and frequency QoS requests are provided.
50 * pm_qos_read_value - Return the current effective constraint value.
55 return READ_ONCE(c->target_value); in pm_qos_read_value()
60 if (plist_head_empty(&c->list)) in pm_qos_get_value()
61 return c->no_constraint_value; in pm_qos_get_value()
63 switch (c->type) { in pm_qos_get_value()
65 return plist_first(&c->list)->prio; in pm_qos_get_value()
68 return plist_last(&c->list)->prio; in pm_qos_get_value()
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/openbmc/linux/block/
H A Dkyber-iosched.c1 // SPDX-License-Identifier: GPL-2.0
3 * The Kyber I/O scheduler. Controls latency by throttling queue depths using
18 #include "blk-mq.h"
19 #include "blk-mq-debugfs.h"
20 #include "blk-mq-sched.h"
54 * Maximum device-wide depth for each scheduling domain.
68 * Default latency targets for each scheduling domain.
89 * to the target latency:
91 * <= 1/4 * target latency
92 * <= 1/2 * target latency
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/openbmc/qemu/block/
H A Daccounting.c37 qemu_mutex_init(&stats->lock); in block_acct_init()
41 stats->account_invalid = true; in block_acct_init()
42 stats->account_failed = true; in block_acct_init()
62 stats->account_invalid = bool_from_onoffauto(account_invalid, in block_acct_setup()
63 stats->account_invalid); in block_acct_setup()
64 stats->account_failed = bool_from_onoffauto(account_failed, in block_acct_setup()
65 stats->account_failed); in block_acct_setup()
71 QSLIST_FOREACH_SAFE(s, &stats->intervals, entries, next) { in block_acct_cleanup()
74 qemu_mutex_destroy(&stats->lock); in block_acct_cleanup()
83 s->interval_length = interval_length; in block_acct_add_interval()
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/openbmc/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
6 * Chen-Yu Tsai <wens@csie.org>
17 ENTRY(sunxi_mc_smp_cluster_cache_enable)
18 .arch armv7-a
20 * Enable cluster-level coherency, in preparation for turning on the MMU.
22 * Also enable regional clock gating and L2 data latency settings for
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
49 /* L2CTRL: L2 data RAM latency */
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
30 ENTRY(get_gic_offset)
59 ENTRY(smp_kick_all_cpus)
71 ENTRY(lowlevel_init)
88 /* Set Wuo bit for RN-I 20 */
95 * Set forced-order mode in RNI-6, RNI-20
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/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
17 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
54 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
59 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
63 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD…
99 … "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.…
104 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
108 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM …
113 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
117 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM R…
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/openbmc/linux/drivers/net/ethernet/amazon/ena/
H A Dena_admin_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
26 /* Additional status is provided in ACQ entry extended_status */
59 /* descriptors and headers are in device memory (a.k.a Low Latency
79 /* completion queue entry for each sq descriptor */
81 /* completion queue entry upon request in sq descriptor */
119 * 1 : ctrl_data - control buffer address valid
120 * 2 : ctrl_data_indirect - control buffer address
142 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
177 /* indicates to the driver which AQ entry has been consumed by the
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/openbmc/qemu/include/sysemu/
H A Dnuma.h5 #include "qapi/qapi-types-machine.h"
6 #include "exec/cpu-common.h"
23 HMAT_LB_LEVELS /* must be the last entry */
34 HMAT_LB_TYPES /* must be the last entry */
66 /* Present the type of data, access/read/write latency or bandwidth. */
93 /* NUMA nodes HMAT Locality Latency and Bandwidth Information */
/openbmc/qemu/tests/qtest/
H A Dbios-tables-test.c10 * See the COPYING file in the top-level directory.
17 * 2. list any changed files in tests/qtest/bios-tables-test-allowed-diff.h
20 * Contributor or ACPI Maintainer (steps 4-7 need to be redone to resolve conflicts
23 * After 1-3 above tests will pass but ignore differences with the expected files.
24 * You will also notice that tests/qtest/bios-tables-test-allowed-diff.h lists
31 * output. If not - disassemble them yourself in any way you like.
32 * Look at the differences - make sure they make sense and match what the
38 * $(SRC_PATH)/tests/data/acpi/rebuild-expected-aml.sh
48 * tests/qtest/bios-tables-test-allowed-diff.h is empty - this will ensure
52 * - patch 1: list changed files in tests/qtest/bios-tables-test-allowed-diff.h.
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