armv8/fsl-layerscape/lowlevel.S

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
30 ENTRY(get_gic_offset)
59 ENTRY(smp_kick_all_cpus)
71 ENTRY(lowlevel_init)
88 	/* Set Wuo bit for RN-I 20 */
95 	 * Set forced-order mode in RNI-6, RNI-20
97 	 * LS2080A family does not support setting forced-order mode,
115 	/* Add fully-coherent masters to DVM domain */
121 	/* Set all RN-I ports to QoS of 15 */
219 	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
262 	ldr     w0, [x1]		/* Region-0 Attributes Register */
270 	ldr     w0, [x1]		/* Region-0 Access Register */
293 	/* Initialize the L2 RAM latency */
296 	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
298 	/* Set L2 data ram latency bits [2:0] */
300 	/* set L2 tag ram latency bits [8:6] */
317 ENTRY(fsl_ocram_init)
325 ENTRY(fsl_clear_ocram)
338 ENTRY(fsl_ocram_clear_ecc_err)
368 	mov	w6, #8			/* HN-F node count */
390 	mov	w6, #8			/* HN-F node count */
404 ENTRY(__asm_flush_l3_dcache)
451 ENTRY(secondary_boot_func)
454 	 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
456 	 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
466 	 * until AFF2_CLUSTERID and AFF3 have non-zero values)
534 ENTRY(secondary_switch_to_el2)
540 ENTRY(secondary_switch_to_el1)
582 	.quad .-secondary_boot_code