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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-cpcap-mapphone.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 interrupt-parent = <&gpio1>;
12 interrupt-controller;
13 #interrupt-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 spi-max-frequency = <9600000>;
17 spi-cs-high;
18 spi-cpol;
19 spi-cpha;
[all …]
H A Domap3-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/input/input.h>
7 #include "omap-gpmc-smsc911x.dtsi"
12 cpu0-supply = <&vcc>;
18 compatible = "regulator-fixed";
19 regulator-name = "hsusb2_vbus";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
23 startup-delay-us = <70000>;
24 enable-active-high;
[all …]
H A Dmotorola-mapphone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "motorola-cpcap-mapphone.dtsi"
10 stdout-path = &uart3;
19 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
20 * then 1023 - 1024 seems to contain mbm.
28 gpio-poweroff {
29 compatible = "gpio-poweroff";
30 pinctrl-0 = <&poweroff_gpio>;
[all …]
/openbmc/linux/Documentation/scsi/
H A Daha152x.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
8 Copyright |copy| 1993-1999 Jürgen Fischer <fischer@norbit.de>
14 bottom-half handler complete()).
27 IRQ interrupt level (9-12; default 11)
28 SCSI_ID scsi id of controller (0-7; default 7)
30 PARITY enable parity checking (0/1; default 1 [on])
31 SYNCHRONOUS enable synchronous transfers (0/1; default 1 [on])
32 DELAY: bus reset delay (default 100)
33 EXT_TRANS: enable extended translation (0/1: default 0 [off])
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795-sony-xperia-m5.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "sony,xperia-m5", "mediatek,mt6795";
15 chassis-type = "handset";
30 reserved_memory: reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
38 no-map;
42 preloader-region@44800000 {
[all …]
H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
[all …]
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,palmas-gpadc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/ti,palmas-gpadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
13 This ADC is often used to provide channels via the io-channels
27 11 DC-DC current probe (how does this work?)
35 const: ti,palmas-gpadc
41 "#io-channel-cells":
44 ti,channel0-current-microamp:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
36 richtek,ld-pulse-delay-us:
[all …]
/openbmc/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
27 #define PHY_EXT_STATUS 0x0F /* Extended Status Register */
29 #define PHY_EXT_PHYSP_CONTROL 0x14 /* Extended PHY Specific Control Register */
31 #define PHY_EXT_PHYSP_STATUS 0x1B /* Extended PHY Specific Status Register */
35 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
40 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
25 * | UTP Extended | FIBER Extended |
26 * ------------------------------------------------------------
27 * | Common Extended |
28 * ------------------------------------------------------------
39 * 2b11 Enable automatic crossover for all modes *default*
67 /* Interrupt enable Register */
98 /* Extended Register's Address Offset Register */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp-prtwd3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
[all …]
H A Dimx6sx-udoo-neo.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 stdout-path = "serial0:115200n8";
16 compatible = "gpio-leds";
18 led-red {
19 label = "udoo-neo:red:mmc";
21 default-state = "off";
22 linux,default-trigger = "mmc0";
25 led-orange {
26 label = "udoo-neo:orange:user";
28 default-state = "keep";
[all …]
/openbmc/linux/include/ufs/
H A Dufs_quirks.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
22 * ufs_dev_quirk - ufs device quirk info
42 * - As soon as SW sees the DL NAC error, it should schedule the error handler
43 * - Error handler would sleep for 50ms to see if there are any fatal errors
45 * - If there are fatal errors then SW does normal error recovery.
46 * - If there are no fatal errors then SW sends the NOP command to device
48 * - If NOP command times out, SW does normal error recovery
49 * - If NOP command succeed, skip the error handling.
52 * enable this quirk to initiate quick error recovery and also silence related
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6375.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
H A Dsdm670-google-sargo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
4 * xiaomi-lavender device tree, and oneplus-common device tree.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
19 /delete-node/ &mpss_region;
20 /delete-node/ &venus_mem;
[all …]
/openbmc/qemu/hw/net/
H A De1000_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
[all …]
/openbmc/linux/sound/hda/ext/
H A Dhdac_ext_controller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * hdac-ext-controller.c - HD-audio extended controller functions.
5 * Copyright (C) 2014-2015 Intel Corp
12 #include <linux/delay.h>
18 * processing pipe helpers - these helpers are useful for dealing with HDA
23 * snd_hdac_ext_bus_ppcap_enable - enable/disable processing pipe capability
25 * @enable: flag to turn on/off the capability
27 void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *bus, bool enable) in snd_hdac_ext_bus_ppcap_enable() argument
30 if (!bus->ppcap) { in snd_hdac_ext_bus_ppcap_enable()
31 dev_err(bus->dev, "Address of PP capability is NULL"); in snd_hdac_ext_bus_ppcap_enable()
[all …]
/openbmc/u-boot/drivers/sound/
H A Dbroadwell_i2s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 u32 reserved0[29]; /* 0x14 - 0x77 */
57 u32 reserved0[5]; /* 0x14 - 0x27 */
78 /* Parity Check Enable */
117 /* SSP Clock Output Enable */
145 /* Receiver Time-out Interrupt */
176 /* Frame Rate Divider Control (0-7) */
186 /* Extended Data Size Select */
188 /* Serial Clock Rate (0-4095) */
191 /* Synchronous Serial Port Enable */
[all …]
/openbmc/linux/net/sched/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 delay, and which ones to drop. This is the job of the queueing
25 To administer these schedulers, you'll need the user-level utilities
31 This Quality of Service (QoS) support will enable you to use
54 in-depth articles.
74 Say Y here if you want to use an n-band priority queue packet
81 tristate "Hardware Multiqueue-aware Multi Band Queuing (MULTIQ)"
83 Say Y here if you want to use an n-band queue packet scheduler
198 Say Y if you want to emulate network delay, loss, and packet
199 re-ordering. This is often useful to simulate networks when
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp151a-prtt1c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */
60 #define SSCR0_EDSS BIT(20) /* Extended data size select */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
66 #define SSCR0_FPCKE BIT(29) /* FIFO packing enable */
70 #define SSCR1_RIE BIT(0) /* Receive FIFO Interrupt Enable */
71 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
72 #define SSCR1_LBM BIT(2) /* Loop-Back Mode */
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]

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