Home
last modified time | relevance | path

Searched +full:edge +full:- +full:triggered (Results 1 – 25 of 393) sorted by relevance

12345678910>>...16

/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
[all …]
H A Dgpio-nmk.txt4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
[all …]
/openbmc/qemu/hw/intc/
H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
24 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
75 /* level-triggered */ in aspeed_vic_set_irq()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Ddlg,da7280.txt4 - compatible: Should be "dlg,da7280".
5 - reg: Specifies the I2C slave address.
7 - interrupt-parent : Specifies the phandle of the interrupt controller to
10 - dlg,actuator-type: Set Actuator type. it should be one of:
11 "LRA" - Linear Resonance Actuator type.
12 "ERM-bar" - Bar type Eccentric Rotating Mass.
13 "ERM-coin" - Coin type Eccentric Rotating Mass.
15 - dlg,const-op-mode: Haptic operation mode for FF_CONSTANT.
17 1 - Direct register override(DRO) mode triggered by i2c(default),
18 2 - PWM data source mode controlled by PWM duty,
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dinterrupt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
52 * configure_irq_trigger() - Configure IRQ triggering
54 * Switch the given interrupt to be level / edge triggered
56 * @param int_num legacy interrupt number (3-7, 9-15)
57 * @param is_level_triggered true for level triggered interrupt, false for
58 * edge triggered interrupt
/openbmc/linux/arch/mips/include/asm/
H A Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
33 /* For read-write shared registers */
37 /* For read-only local registers */
42 /* For read-write local registers */
47 /* For read-only shared per-interrupt registers */
60 /* For read-write shared per-interrupt registers */
71 /* For read-only local per-interrupt registers */
78 /* For read-write local per-interrupt registers */
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dintc-2.c2 * intc-2.c
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
10 * The external 7 fixed interrupts are part of the Edge Port unit of these
11 * ColdFire parts. They can be configured as level or edge triggered.
13 * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
37 * The EDGE Port interrupts are the fixed 7 external interrupts.
41 #define EINT1 65 /* EDGE Port interrupt 1 */
42 #define EINT7 71 /* EDGE Port interrupt 7 */
52 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_mask()
[all …]
H A Dintc-5272.c2 * intc.c -- interrupt controller or ColdFire 5272 SoC
24 * ColdFire interrupt controller - it truly is completely different.
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
44 static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
83 unsigned int irq = d->irq; in intc_irq_mask()
87 irq -= MCFINT_VECBASE; in intc_irq_mask()
95 unsigned int irq = d->irq; in intc_irq_unmask()
99 irq -= MCFINT_VECBASE; in intc_irq_unmask()
107 unsigned int irq = d->irq; in intc_irq_ack()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dopencores,or1k-pic.txt5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
8 with the non-spec compliant or1200 type implementation.
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
19 intc: interrupt-controller {
20 compatible = "opencores,or1k-pic-level";
21 interrupt-controller;
[all …]
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
30 core_intc: core-interrupt-controller {
[all …]
H A Datmel,aic.txt4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
22 - reg: Should contain AIC registers location and length
[all …]
H A Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
[all …]
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
18 to be driven per N output. An Interrupt Router can either handle edge
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
[all …]
/openbmc/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra20-gpio.txt4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dpcmmio.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for Winsystems PC-104 based multifunction IO board.
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: A driver for the PCM-MIO multifunction board
13 * Devices: [Winsystems] PCM-MIO (pcmmio)
15 * Updated: Wed, May 16 2007 16:21:10 -0500
18 * A driver for the PCM-MIO multifunction board from Winsystems. This
19 * is a PC-104 based I/O board. It contains four subdevices:
21 * subdevice 0 - 16 channels of 16-bit AI
22 * subdevice 1 - 8 channels of 16-bit AO
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-power.json28 "PublicDescription": "Cycles spent in phase-shedding power state 0",
36 "PublicDescription": "Cycles spent in phase-shedding power state 1",
44 "PublicDescription": "Cycles spent in phase-shedding power state 2",
52 "PublicDescription": "Cycles spent in phase-shedding power state 3",
99 …"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding…
103 "BriefDescription": "Package C State Residency - C0",
107 …s when the package was in C0. This event can be used in conjunction with edge detect to count C0 …
111 "BriefDescription": "Package C State Residency - C2E",
115 … when the package was in C2E. This event can be used in conjunction with edge detect to count C2E…
119 "BriefDescription": "Package C State Residency - C3",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-power.json28 "PublicDescription": "Cycles spent in phase-shedding power state 0",
36 "PublicDescription": "Cycles spent in phase-shedding power state 1",
44 "PublicDescription": "Cycles spent in phase-shedding power state 2",
52 "PublicDescription": "Cycles spent in phase-shedding power state 3",
99 …"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding…
103 "BriefDescription": "Package C State Residency - C0",
107 …s when the package was in C0. This event can be used in conjunction with edge detect to count C0 …
111 "BriefDescription": "Package C State Residency - C2E",
115 … when the package was in C2E. This event can be used in conjunction with edge detect to count C2E…
119 "BriefDescription": "Package C State Residency - C3",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-power.json28 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
36 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
44 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
52 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
106 …ry Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase she…
110 "BriefDescription": "Package C State Residency - C0",
114 …ge C State Residency - C0 : Counts the number of cycles when the package was in C0. This event ca…
118 "BriefDescription": "Package C State Residency - C2E",
122 …e C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event c…
126 "BriefDescription": "Package C State Residency - C3",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-power.json27 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
35 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
43 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
51 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
105 …ry Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase she…
109 "BriefDescription": "Package C State Residency - C0",
113 …ge C State Residency - C0 : Counts the number of cycles when the package was in C0. This event ca…
117 "BriefDescription": "Package C State Residency - C2E",
121 …e C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event c…
125 "BriefDescription": "Package C State Residency - C3",
[all …]

12345678910>>...16