| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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| /openbmc/linux/drivers/mtd/nand/ |
| H A D | ecc-mtk.c | 3 * MTK ECC controller driver.
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
150 if (dec & ecc->sectors) { in mtk_ecc_irq()
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| H A D | ecc.c | 3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
28 * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on
30 * engine, this step may involve to derive the ECC bytes and place
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| H A D | ecc-sw-bch.c | 3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
44 * @read_ecc: ECC bytes from the chip
45 * @calc_ecc: ECC calculated from the raw data
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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| /openbmc/linux/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_ecc.c | 3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
37 * @ecc: ECC device.
38 * @params: ECC parameters.
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| H A D | ingenic_nand_drv.c | 44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
95 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
96 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
102 .ecc = qi_lb60_ooblayout_ecc,
110 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
112 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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| H A D | jz4740_ecc.c | 3 * JZ4740 ECC controller driver
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
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| /openbmc/docs/designs/ |
| H A D | ecc-dbus-sel.md | 1 ### ECC Error SEL for BMC
9 The IPMI SELs only define memory Error Correction Code (ECC) errors for host
12 The aim of this proposal is to record ECC events from the BMC in the IPMI System
13 Event Log (SEL). Whenever ECC occurs, the BMC generates an event with the
18 The IPMI specification defines memory system event log about ECC/other
19 correctable or ECC/other uncorrectable and whether ECC/other correctable memory
20 error logging limits are reached.[1]. The BMC ECC SEL will follow IPMI SEL
21 format and creates BMC memory ECC event log.
24 event log. It does not yet support the BMC ECC SEL feature in OpenBMC project.
25 Therefore, the memory ECC information will be registered to D-Bus and generate
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | omap_gpmc.c | 93 * gen_true_ecc - This function will generate true ECC value, which
96 * @ecc_buf: buffer to store ecc code
98 * @return: re-formatted ECC value
107 * omap_correct_data - Compares the ecc read from nand spare area with ECC
115 * @read_ecc: ecc read from nand flash
116 * @calc_ecc: ecc read from ECC registers
127 /* Regenerate the orginal ECC */ in omap_correct_data()
130 /* Get the XOR of real ecc */ in omap_correct_data()
144 printf("Error: Ecc is wrong\n"); in omap_correct_data()
145 /* ECC itself is corrupted */ in omap_correct_data()
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| H A D | fsmc_nand.c | 24 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
62 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
97 * ECC placement definitions in oobfree type format
98 * There are 13 bytes of ecc for every 512 byte block and it has to be read
101 * Managing the ecc bytes in the following way makes it easier for software to
102 * read ecc bytes consecutive to data bytes. This way is similar to
196 /* The calculated ecc is actually the correction index in data */ in fsmc_bch8_correct_data()
209 * would result in an ecc error because the oob data is also in fsmc_bch8_correct_data()
210 * erased to FF and the calculated ecc for an FF data is not in fsmc_bch8_correct_data()
261 const u_char *data, u_char *ecc) in fsmc_read_hwecc() argument
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| H A D | zynq_nand.c | 36 (0x1 << 6)) /* Disable ECC interrupt */
54 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
55 (0x1 << 4) | /* ECC read at end of page */ \
83 /* ECC block registers bit position and bit mask */
84 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
85 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
212 /* bbt decriptors for chips with on-die ECC and
238 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
286 /* Wait till the ECC operation is complete */ in zynq_nand_init_nand_flash()
301 * zynq_nand_calculate_hwecc - Calculate Hardware ECC
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| H A D | nand_base.c | 21 * if we have HW ECC support.
1134 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1138 * @ecc: ECC buffer
1139 * @ecclen: ECC length
1144 * Check if a data buffer and its associated ECC and OOB data contains only
1151 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1152 * different from the NAND page size. When fixing bitflips, ECC engines will
1159 * the payload data but also their associated ECC data, because a user might
1161 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1164 * data are protected by the ECC engine.
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| H A D | sunxi_nand.c | 212 * sunxi HW ECC infos: stores information related to HW ECC support
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
215 * @layout: the OOB layout depending on the ECC requirements and the
216 * selected ECC mode
684 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc) in sunxi_nfc_randomizer_state() argument
692 if (ecc) { in sunxi_nfc_randomizer_state()
703 int page, bool ecc) in sunxi_nfc_randomizer_config() argument
714 state = sunxi_nfc_randomizer_state(mtd, page, ecc); in sunxi_nfc_randomizer_config()
753 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
755 sunxi_nfc_randomizer_config(mtd, page, ecc); in sunxi_nfc_randomizer_write_buf()
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| H A D | Kconfig | 15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
88 of OOB area before last ECC sector data starts. This is potentially
102 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
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| H A D | nand_bch.c | 3 * This file provides ECC correction for more than 1 bit per block of data,
24 * @ecclayout: private ecc layout for this BCH configuration
26 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
36 * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
39 * @code: output buffer with ECC
45 struct nand_bch_control *nbc = chip->ecc.priv; in nand_bch_calculate_ecc()
48 memset(code, 0, chip->ecc.bytes); in nand_bch_calculate_ecc()
49 encode_bch(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
52 for (i = 0; i < chip->ecc.bytes; i++) in nand_bch_calculate_ecc()
62 * @read_ecc: ECC from the chip
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| /openbmc/linux/drivers/dma/ti/ |
| H A D | edma.c | 219 struct edma_cc *ecc; member
300 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
302 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
305 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
307 __raw_writel(val, ecc->base + offset); in edma_write()
310 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
313 unsigned val = edma_read(ecc, offset); in edma_modify()
317 edma_write(ecc, offset, val); in edma_modify()
320 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
322 unsigned val = edma_read(ecc, offset); in edma_or()
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| /openbmc/u-boot/arch/arm/mach-uniphier/boot-device/ |
| H A D | boot-device-ld4.c | 16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
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| H A D | boot-device-pro5.c | 15 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
27 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
28 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
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| H A D | boot-device-pxs2.c | 15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
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| H A D | boot-device-ld11.c | 15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
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| /openbmc/linux/drivers/edac/ |
| H A D | mce_amd.c | 82 "Fill ECC error on data fills", /* xec = 0x4 */
87 "WCC Tag ECC error",
88 "WCC Data ECC error",
90 "VB Data ECC or parity error",
91 "L2 Tag ECC error", /* xec = 0x10 */
92 "Hard L2 Tag ECC error",
99 "DRAM ECC error detected on the NB",
107 "DRAM ECC error detected on the NB",
114 "L3 data cache ECC error", /* xec = 0x1c */
117 "ECC Error in the Probe Filter directory"
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_micron.c | 15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
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| H A D | omap2.c | 18 #include <linux/mtd/nand-ecc-sw-bch.h>
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
623 * gen_true_ecc - This function will generate true ECC value
624 * @ecc_buf: buffer to store ecc code
626 * This generated true ECC value can be used when correcting
644 * @ecc_data1: ecc code from nand spare area
645 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
648 * This function compares two ECC's and indicates if there is an error.
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
37 nand-use-soft-ecc-engine:
38 description: Use a software ECC engine.
41 nand-no-ecc-engine:
42 description: Do not use any ECC correction.
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| H A D | rockchip,nand-controller.yaml | 66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
75 The ECC configurations that can be supported are as follows.
76 NFC v600 ECC 16, 24, 40, 60
79 NFC v622 ECC 16, 24, 40, 60
82 NFC v800 ECC 16
85 NFC v900 ECC 16, 40, 60, 70
96 The NFC driver need this information to select ECC
100 rockchip,boot-ecc-strength:
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