14fd62f15SChuanhong Guo // SPDX-License-Identifier: GPL-2.0 OR MIT
24fd62f15SChuanhong Guo /*
34fd62f15SChuanhong Guo * MTK ECC controller driver.
44fd62f15SChuanhong Guo * Copyright (C) 2016 MediaTek Inc.
54fd62f15SChuanhong Guo * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
64fd62f15SChuanhong Guo * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
74fd62f15SChuanhong Guo */
84fd62f15SChuanhong Guo
94fd62f15SChuanhong Guo #include <linux/platform_device.h>
104fd62f15SChuanhong Guo #include <linux/dma-mapping.h>
114fd62f15SChuanhong Guo #include <linux/interrupt.h>
124fd62f15SChuanhong Guo #include <linux/clk.h>
134fd62f15SChuanhong Guo #include <linux/module.h>
144fd62f15SChuanhong Guo #include <linux/iopoll.h>
154fd62f15SChuanhong Guo #include <linux/of.h>
164fd62f15SChuanhong Guo #include <linux/of_platform.h>
174fd62f15SChuanhong Guo #include <linux/mutex.h>
184fd62f15SChuanhong Guo #include <linux/mtd/nand-ecc-mtk.h>
194fd62f15SChuanhong Guo
204fd62f15SChuanhong Guo #define ECC_IDLE_MASK BIT(0)
214fd62f15SChuanhong Guo #define ECC_IRQ_EN BIT(0)
224fd62f15SChuanhong Guo #define ECC_PG_IRQ_SEL BIT(1)
234fd62f15SChuanhong Guo #define ECC_OP_ENABLE (1)
244fd62f15SChuanhong Guo #define ECC_OP_DISABLE (0)
254fd62f15SChuanhong Guo
264fd62f15SChuanhong Guo #define ECC_ENCCON (0x00)
274fd62f15SChuanhong Guo #define ECC_ENCCNFG (0x04)
284fd62f15SChuanhong Guo #define ECC_MS_SHIFT (16)
294fd62f15SChuanhong Guo #define ECC_ENCDIADDR (0x08)
304fd62f15SChuanhong Guo #define ECC_ENCIDLE (0x0C)
314fd62f15SChuanhong Guo #define ECC_DECCON (0x100)
324fd62f15SChuanhong Guo #define ECC_DECCNFG (0x104)
334fd62f15SChuanhong Guo #define DEC_EMPTY_EN BIT(31)
344fd62f15SChuanhong Guo #define DEC_CNFG_CORRECT (0x3 << 12)
354fd62f15SChuanhong Guo #define ECC_DECIDLE (0x10C)
364fd62f15SChuanhong Guo #define ECC_DECENUM0 (0x114)
374fd62f15SChuanhong Guo
384fd62f15SChuanhong Guo #define ECC_TIMEOUT (500000)
394fd62f15SChuanhong Guo
404fd62f15SChuanhong Guo #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
414fd62f15SChuanhong Guo #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
424fd62f15SChuanhong Guo
43*4d21176fSXiangsheng Hou #define ECC_ERRMASK_MT7622 GENMASK(4, 0)
44*4d21176fSXiangsheng Hou #define ECC_ERRMASK_MT2701 GENMASK(5, 0)
45*4d21176fSXiangsheng Hou #define ECC_ERRMASK_MT2712 GENMASK(6, 0)
46*4d21176fSXiangsheng Hou
474fd62f15SChuanhong Guo struct mtk_ecc_caps {
484fd62f15SChuanhong Guo u32 err_mask;
49d3353719SLinus Torvalds u32 err_shift;
504fd62f15SChuanhong Guo const u8 *ecc_strength;
514fd62f15SChuanhong Guo const u32 *ecc_regs;
524fd62f15SChuanhong Guo u8 num_ecc_strength;
534fd62f15SChuanhong Guo u8 ecc_mode_shift;
544fd62f15SChuanhong Guo u32 parity_bits;
554fd62f15SChuanhong Guo int pg_irq_sel;
564fd62f15SChuanhong Guo };
574fd62f15SChuanhong Guo
584fd62f15SChuanhong Guo struct mtk_ecc {
594fd62f15SChuanhong Guo struct device *dev;
604fd62f15SChuanhong Guo const struct mtk_ecc_caps *caps;
614fd62f15SChuanhong Guo void __iomem *regs;
624fd62f15SChuanhong Guo struct clk *clk;
634fd62f15SChuanhong Guo
644fd62f15SChuanhong Guo struct completion done;
654fd62f15SChuanhong Guo struct mutex lock;
664fd62f15SChuanhong Guo u32 sectors;
674fd62f15SChuanhong Guo
684fd62f15SChuanhong Guo u8 *eccdata;
694fd62f15SChuanhong Guo };
704fd62f15SChuanhong Guo
714fd62f15SChuanhong Guo /* ecc strength that each IP supports */
724fd62f15SChuanhong Guo static const u8 ecc_strength_mt2701[] = {
734fd62f15SChuanhong Guo 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
744fd62f15SChuanhong Guo 40, 44, 48, 52, 56, 60
754fd62f15SChuanhong Guo };
764fd62f15SChuanhong Guo
774fd62f15SChuanhong Guo static const u8 ecc_strength_mt2712[] = {
784fd62f15SChuanhong Guo 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
794fd62f15SChuanhong Guo 40, 44, 48, 52, 56, 60, 68, 72, 80
804fd62f15SChuanhong Guo };
814fd62f15SChuanhong Guo
824fd62f15SChuanhong Guo static const u8 ecc_strength_mt7622[] = {
83d3353719SLinus Torvalds 4, 6, 8, 10, 12
844fd62f15SChuanhong Guo };
854fd62f15SChuanhong Guo
86*4d21176fSXiangsheng Hou static const u8 ecc_strength_mt7986[] = {
87*4d21176fSXiangsheng Hou 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
88*4d21176fSXiangsheng Hou };
89*4d21176fSXiangsheng Hou
904fd62f15SChuanhong Guo enum mtk_ecc_regs {
914fd62f15SChuanhong Guo ECC_ENCPAR00,
924fd62f15SChuanhong Guo ECC_ENCIRQ_EN,
934fd62f15SChuanhong Guo ECC_ENCIRQ_STA,
944fd62f15SChuanhong Guo ECC_DECDONE,
954fd62f15SChuanhong Guo ECC_DECIRQ_EN,
964fd62f15SChuanhong Guo ECC_DECIRQ_STA,
974fd62f15SChuanhong Guo };
984fd62f15SChuanhong Guo
994fd62f15SChuanhong Guo static int mt2701_ecc_regs[] = {
1004fd62f15SChuanhong Guo [ECC_ENCPAR00] = 0x10,
1014fd62f15SChuanhong Guo [ECC_ENCIRQ_EN] = 0x80,
1024fd62f15SChuanhong Guo [ECC_ENCIRQ_STA] = 0x84,
1034fd62f15SChuanhong Guo [ECC_DECDONE] = 0x124,
1044fd62f15SChuanhong Guo [ECC_DECIRQ_EN] = 0x200,
1054fd62f15SChuanhong Guo [ECC_DECIRQ_STA] = 0x204,
1064fd62f15SChuanhong Guo };
1074fd62f15SChuanhong Guo
1084fd62f15SChuanhong Guo static int mt2712_ecc_regs[] = {
1094fd62f15SChuanhong Guo [ECC_ENCPAR00] = 0x300,
1104fd62f15SChuanhong Guo [ECC_ENCIRQ_EN] = 0x80,
1114fd62f15SChuanhong Guo [ECC_ENCIRQ_STA] = 0x84,
1124fd62f15SChuanhong Guo [ECC_DECDONE] = 0x124,
1134fd62f15SChuanhong Guo [ECC_DECIRQ_EN] = 0x200,
1144fd62f15SChuanhong Guo [ECC_DECIRQ_STA] = 0x204,
1154fd62f15SChuanhong Guo };
1164fd62f15SChuanhong Guo
1174fd62f15SChuanhong Guo static int mt7622_ecc_regs[] = {
1184fd62f15SChuanhong Guo [ECC_ENCPAR00] = 0x10,
1194fd62f15SChuanhong Guo [ECC_ENCIRQ_EN] = 0x30,
1204fd62f15SChuanhong Guo [ECC_ENCIRQ_STA] = 0x34,
1214fd62f15SChuanhong Guo [ECC_DECDONE] = 0x11c,
1224fd62f15SChuanhong Guo [ECC_DECIRQ_EN] = 0x140,
1234fd62f15SChuanhong Guo [ECC_DECIRQ_STA] = 0x144,
1244fd62f15SChuanhong Guo };
1254fd62f15SChuanhong Guo
mtk_ecc_wait_idle(struct mtk_ecc * ecc,enum mtk_ecc_operation op)1264fd62f15SChuanhong Guo static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
1274fd62f15SChuanhong Guo enum mtk_ecc_operation op)
1284fd62f15SChuanhong Guo {
1294fd62f15SChuanhong Guo struct device *dev = ecc->dev;
1304fd62f15SChuanhong Guo u32 val;
1314fd62f15SChuanhong Guo int ret;
1324fd62f15SChuanhong Guo
1334fd62f15SChuanhong Guo ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
1344fd62f15SChuanhong Guo val & ECC_IDLE_MASK,
1354fd62f15SChuanhong Guo 10, ECC_TIMEOUT);
1364fd62f15SChuanhong Guo if (ret)
1374fd62f15SChuanhong Guo dev_warn(dev, "%s NOT idle\n",
1384fd62f15SChuanhong Guo op == ECC_ENCODE ? "encoder" : "decoder");
1394fd62f15SChuanhong Guo }
1404fd62f15SChuanhong Guo
mtk_ecc_irq(int irq,void * id)1414fd62f15SChuanhong Guo static irqreturn_t mtk_ecc_irq(int irq, void *id)
1424fd62f15SChuanhong Guo {
1434fd62f15SChuanhong Guo struct mtk_ecc *ecc = id;
1444fd62f15SChuanhong Guo u32 dec, enc;
1454fd62f15SChuanhong Guo
1464fd62f15SChuanhong Guo dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
1474fd62f15SChuanhong Guo & ECC_IRQ_EN;
1484fd62f15SChuanhong Guo if (dec) {
1494fd62f15SChuanhong Guo dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
1504fd62f15SChuanhong Guo if (dec & ecc->sectors) {
1514fd62f15SChuanhong Guo /*
1524fd62f15SChuanhong Guo * Clear decode IRQ status once again to ensure that
1534fd62f15SChuanhong Guo * there will be no extra IRQ.
1544fd62f15SChuanhong Guo */
1554fd62f15SChuanhong Guo readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
1564fd62f15SChuanhong Guo ecc->sectors = 0;
1574fd62f15SChuanhong Guo complete(&ecc->done);
1584fd62f15SChuanhong Guo } else {
1594fd62f15SChuanhong Guo return IRQ_HANDLED;
1604fd62f15SChuanhong Guo }
1614fd62f15SChuanhong Guo } else {
1624fd62f15SChuanhong Guo enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
1634fd62f15SChuanhong Guo & ECC_IRQ_EN;
1644fd62f15SChuanhong Guo if (enc)
1654fd62f15SChuanhong Guo complete(&ecc->done);
1664fd62f15SChuanhong Guo else
1674fd62f15SChuanhong Guo return IRQ_NONE;
1684fd62f15SChuanhong Guo }
1694fd62f15SChuanhong Guo
1704fd62f15SChuanhong Guo return IRQ_HANDLED;
1714fd62f15SChuanhong Guo }
1724fd62f15SChuanhong Guo
mtk_ecc_config(struct mtk_ecc * ecc,struct mtk_ecc_config * config)1734fd62f15SChuanhong Guo static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
1744fd62f15SChuanhong Guo {
1754fd62f15SChuanhong Guo u32 ecc_bit, dec_sz, enc_sz;
1764fd62f15SChuanhong Guo u32 reg, i;
1774fd62f15SChuanhong Guo
1784fd62f15SChuanhong Guo for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
1794fd62f15SChuanhong Guo if (ecc->caps->ecc_strength[i] == config->strength)
1804fd62f15SChuanhong Guo break;
1814fd62f15SChuanhong Guo }
1824fd62f15SChuanhong Guo
1834fd62f15SChuanhong Guo if (i == ecc->caps->num_ecc_strength) {
1844fd62f15SChuanhong Guo dev_err(ecc->dev, "invalid ecc strength %d\n",
1854fd62f15SChuanhong Guo config->strength);
1864fd62f15SChuanhong Guo return -EINVAL;
1874fd62f15SChuanhong Guo }
1884fd62f15SChuanhong Guo
1894fd62f15SChuanhong Guo ecc_bit = i;
1904fd62f15SChuanhong Guo
1914fd62f15SChuanhong Guo if (config->op == ECC_ENCODE) {
1924fd62f15SChuanhong Guo /* configure ECC encoder (in bits) */
1934fd62f15SChuanhong Guo enc_sz = config->len << 3;
1944fd62f15SChuanhong Guo
1954fd62f15SChuanhong Guo reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
1964fd62f15SChuanhong Guo reg |= (enc_sz << ECC_MS_SHIFT);
1974fd62f15SChuanhong Guo writel(reg, ecc->regs + ECC_ENCCNFG);
1984fd62f15SChuanhong Guo
1994fd62f15SChuanhong Guo if (config->mode != ECC_NFI_MODE)
2004fd62f15SChuanhong Guo writel(lower_32_bits(config->addr),
2014fd62f15SChuanhong Guo ecc->regs + ECC_ENCDIADDR);
2024fd62f15SChuanhong Guo
2034fd62f15SChuanhong Guo } else {
2044fd62f15SChuanhong Guo /* configure ECC decoder (in bits) */
2054fd62f15SChuanhong Guo dec_sz = (config->len << 3) +
2064fd62f15SChuanhong Guo config->strength * ecc->caps->parity_bits;
2074fd62f15SChuanhong Guo
2084fd62f15SChuanhong Guo reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
2094fd62f15SChuanhong Guo reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
2104fd62f15SChuanhong Guo reg |= DEC_EMPTY_EN;
2114fd62f15SChuanhong Guo writel(reg, ecc->regs + ECC_DECCNFG);
2124fd62f15SChuanhong Guo
2134fd62f15SChuanhong Guo if (config->sectors)
2144fd62f15SChuanhong Guo ecc->sectors = 1 << (config->sectors - 1);
2154fd62f15SChuanhong Guo }
2164fd62f15SChuanhong Guo
2174fd62f15SChuanhong Guo return 0;
2184fd62f15SChuanhong Guo }
2194fd62f15SChuanhong Guo
mtk_ecc_get_stats(struct mtk_ecc * ecc,struct mtk_ecc_stats * stats,int sectors)2204fd62f15SChuanhong Guo void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
2214fd62f15SChuanhong Guo int sectors)
2224fd62f15SChuanhong Guo {
2234fd62f15SChuanhong Guo u32 offset, i, err;
2244fd62f15SChuanhong Guo u32 bitflips = 0;
2254fd62f15SChuanhong Guo
2264fd62f15SChuanhong Guo stats->corrected = 0;
2274fd62f15SChuanhong Guo stats->failed = 0;
2284fd62f15SChuanhong Guo
2294fd62f15SChuanhong Guo for (i = 0; i < sectors; i++) {
2304fd62f15SChuanhong Guo offset = (i >> 2) << 2;
2314fd62f15SChuanhong Guo err = readl(ecc->regs + ECC_DECENUM0 + offset);
232d3353719SLinus Torvalds err = err >> ((i % 4) * ecc->caps->err_shift);
2334fd62f15SChuanhong Guo err &= ecc->caps->err_mask;
2344fd62f15SChuanhong Guo if (err == ecc->caps->err_mask) {
2354fd62f15SChuanhong Guo /* uncorrectable errors */
2364fd62f15SChuanhong Guo stats->failed++;
2374fd62f15SChuanhong Guo continue;
2384fd62f15SChuanhong Guo }
2394fd62f15SChuanhong Guo
2404fd62f15SChuanhong Guo stats->corrected += err;
2414fd62f15SChuanhong Guo bitflips = max_t(u32, bitflips, err);
2424fd62f15SChuanhong Guo }
2434fd62f15SChuanhong Guo
2444fd62f15SChuanhong Guo stats->bitflips = bitflips;
2454fd62f15SChuanhong Guo }
2464fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_get_stats);
2474fd62f15SChuanhong Guo
mtk_ecc_release(struct mtk_ecc * ecc)2484fd62f15SChuanhong Guo void mtk_ecc_release(struct mtk_ecc *ecc)
2494fd62f15SChuanhong Guo {
2504fd62f15SChuanhong Guo clk_disable_unprepare(ecc->clk);
2514fd62f15SChuanhong Guo put_device(ecc->dev);
2524fd62f15SChuanhong Guo }
2534fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_release);
2544fd62f15SChuanhong Guo
mtk_ecc_hw_init(struct mtk_ecc * ecc)2554fd62f15SChuanhong Guo static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
2564fd62f15SChuanhong Guo {
2574fd62f15SChuanhong Guo mtk_ecc_wait_idle(ecc, ECC_ENCODE);
2584fd62f15SChuanhong Guo writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
2594fd62f15SChuanhong Guo
2604fd62f15SChuanhong Guo mtk_ecc_wait_idle(ecc, ECC_DECODE);
2614fd62f15SChuanhong Guo writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
2624fd62f15SChuanhong Guo }
2634fd62f15SChuanhong Guo
mtk_ecc_get(struct device_node * np)2644fd62f15SChuanhong Guo static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
2654fd62f15SChuanhong Guo {
2664fd62f15SChuanhong Guo struct platform_device *pdev;
2674fd62f15SChuanhong Guo struct mtk_ecc *ecc;
2684fd62f15SChuanhong Guo
2694fd62f15SChuanhong Guo pdev = of_find_device_by_node(np);
2704fd62f15SChuanhong Guo if (!pdev)
2714fd62f15SChuanhong Guo return ERR_PTR(-EPROBE_DEFER);
2724fd62f15SChuanhong Guo
2734fd62f15SChuanhong Guo ecc = platform_get_drvdata(pdev);
2744fd62f15SChuanhong Guo if (!ecc) {
2754fd62f15SChuanhong Guo put_device(&pdev->dev);
2764fd62f15SChuanhong Guo return ERR_PTR(-EPROBE_DEFER);
2774fd62f15SChuanhong Guo }
2784fd62f15SChuanhong Guo
2794fd62f15SChuanhong Guo clk_prepare_enable(ecc->clk);
2804fd62f15SChuanhong Guo mtk_ecc_hw_init(ecc);
2814fd62f15SChuanhong Guo
2824fd62f15SChuanhong Guo return ecc;
2834fd62f15SChuanhong Guo }
2844fd62f15SChuanhong Guo
of_mtk_ecc_get(struct device_node * of_node)2854fd62f15SChuanhong Guo struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
2864fd62f15SChuanhong Guo {
2874fd62f15SChuanhong Guo struct mtk_ecc *ecc = NULL;
2884fd62f15SChuanhong Guo struct device_node *np;
2894fd62f15SChuanhong Guo
2904c5bf4b5SChuanhong Guo np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
2914c5bf4b5SChuanhong Guo /* for backward compatibility */
2924c5bf4b5SChuanhong Guo if (!np)
2934fd62f15SChuanhong Guo np = of_parse_phandle(of_node, "ecc-engine", 0);
2944fd62f15SChuanhong Guo if (np) {
2954fd62f15SChuanhong Guo ecc = mtk_ecc_get(np);
2964fd62f15SChuanhong Guo of_node_put(np);
2974fd62f15SChuanhong Guo }
2984fd62f15SChuanhong Guo
2994fd62f15SChuanhong Guo return ecc;
3004fd62f15SChuanhong Guo }
3014fd62f15SChuanhong Guo EXPORT_SYMBOL(of_mtk_ecc_get);
3024fd62f15SChuanhong Guo
mtk_ecc_enable(struct mtk_ecc * ecc,struct mtk_ecc_config * config)3034fd62f15SChuanhong Guo int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
3044fd62f15SChuanhong Guo {
3054fd62f15SChuanhong Guo enum mtk_ecc_operation op = config->op;
3064fd62f15SChuanhong Guo u16 reg_val;
3074fd62f15SChuanhong Guo int ret;
3084fd62f15SChuanhong Guo
3094fd62f15SChuanhong Guo ret = mutex_lock_interruptible(&ecc->lock);
3104fd62f15SChuanhong Guo if (ret) {
3114fd62f15SChuanhong Guo dev_err(ecc->dev, "interrupted when attempting to lock\n");
3124fd62f15SChuanhong Guo return ret;
3134fd62f15SChuanhong Guo }
3144fd62f15SChuanhong Guo
3154fd62f15SChuanhong Guo mtk_ecc_wait_idle(ecc, op);
3164fd62f15SChuanhong Guo
3174fd62f15SChuanhong Guo ret = mtk_ecc_config(ecc, config);
3184fd62f15SChuanhong Guo if (ret) {
3194fd62f15SChuanhong Guo mutex_unlock(&ecc->lock);
3204fd62f15SChuanhong Guo return ret;
3214fd62f15SChuanhong Guo }
3224fd62f15SChuanhong Guo
3234fd62f15SChuanhong Guo if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
3244fd62f15SChuanhong Guo init_completion(&ecc->done);
3254fd62f15SChuanhong Guo reg_val = ECC_IRQ_EN;
3264fd62f15SChuanhong Guo /*
3274fd62f15SChuanhong Guo * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
3284fd62f15SChuanhong Guo * means this chip can only generate one ecc irq during page
3294fd62f15SChuanhong Guo * read / write. If is 0, generate one ecc irq each ecc step.
3304fd62f15SChuanhong Guo */
3314fd62f15SChuanhong Guo if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
3324fd62f15SChuanhong Guo reg_val |= ECC_PG_IRQ_SEL;
3334fd62f15SChuanhong Guo if (op == ECC_ENCODE)
3344fd62f15SChuanhong Guo writew(reg_val, ecc->regs +
3354fd62f15SChuanhong Guo ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
3364fd62f15SChuanhong Guo else
3374fd62f15SChuanhong Guo writew(reg_val, ecc->regs +
3384fd62f15SChuanhong Guo ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
3394fd62f15SChuanhong Guo }
3404fd62f15SChuanhong Guo
3414fd62f15SChuanhong Guo writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
3424fd62f15SChuanhong Guo
3434fd62f15SChuanhong Guo return 0;
3444fd62f15SChuanhong Guo }
3454fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_enable);
3464fd62f15SChuanhong Guo
mtk_ecc_disable(struct mtk_ecc * ecc)3474fd62f15SChuanhong Guo void mtk_ecc_disable(struct mtk_ecc *ecc)
3484fd62f15SChuanhong Guo {
3494fd62f15SChuanhong Guo enum mtk_ecc_operation op = ECC_ENCODE;
3504fd62f15SChuanhong Guo
3514fd62f15SChuanhong Guo /* find out the running operation */
3524fd62f15SChuanhong Guo if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
3534fd62f15SChuanhong Guo op = ECC_DECODE;
3544fd62f15SChuanhong Guo
3554fd62f15SChuanhong Guo /* disable it */
3564fd62f15SChuanhong Guo mtk_ecc_wait_idle(ecc, op);
3574fd62f15SChuanhong Guo if (op == ECC_DECODE) {
3584fd62f15SChuanhong Guo /*
3594fd62f15SChuanhong Guo * Clear decode IRQ status in case there is a timeout to wait
3604fd62f15SChuanhong Guo * decode IRQ.
3614fd62f15SChuanhong Guo */
3624fd62f15SChuanhong Guo readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
3634fd62f15SChuanhong Guo writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
3644fd62f15SChuanhong Guo } else {
3654fd62f15SChuanhong Guo writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
3664fd62f15SChuanhong Guo }
3674fd62f15SChuanhong Guo
3684fd62f15SChuanhong Guo writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
3694fd62f15SChuanhong Guo
3704fd62f15SChuanhong Guo mutex_unlock(&ecc->lock);
3714fd62f15SChuanhong Guo }
3724fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_disable);
3734fd62f15SChuanhong Guo
mtk_ecc_wait_done(struct mtk_ecc * ecc,enum mtk_ecc_operation op)3744fd62f15SChuanhong Guo int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
3754fd62f15SChuanhong Guo {
3764fd62f15SChuanhong Guo int ret;
3774fd62f15SChuanhong Guo
3784fd62f15SChuanhong Guo ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
3794fd62f15SChuanhong Guo if (!ret) {
3804fd62f15SChuanhong Guo dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
3814fd62f15SChuanhong Guo (op == ECC_ENCODE) ? "encoder" : "decoder");
3824fd62f15SChuanhong Guo return -ETIMEDOUT;
3834fd62f15SChuanhong Guo }
3844fd62f15SChuanhong Guo
3854fd62f15SChuanhong Guo return 0;
3864fd62f15SChuanhong Guo }
3874fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_wait_done);
3884fd62f15SChuanhong Guo
mtk_ecc_encode(struct mtk_ecc * ecc,struct mtk_ecc_config * config,u8 * data,u32 bytes)3894fd62f15SChuanhong Guo int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
3904fd62f15SChuanhong Guo u8 *data, u32 bytes)
3914fd62f15SChuanhong Guo {
3924fd62f15SChuanhong Guo dma_addr_t addr;
3934fd62f15SChuanhong Guo u32 len;
3944fd62f15SChuanhong Guo int ret;
3954fd62f15SChuanhong Guo
3964fd62f15SChuanhong Guo addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
3974fd62f15SChuanhong Guo ret = dma_mapping_error(ecc->dev, addr);
3984fd62f15SChuanhong Guo if (ret) {
3994fd62f15SChuanhong Guo dev_err(ecc->dev, "dma mapping error\n");
4004fd62f15SChuanhong Guo return -EINVAL;
4014fd62f15SChuanhong Guo }
4024fd62f15SChuanhong Guo
4034fd62f15SChuanhong Guo config->op = ECC_ENCODE;
4044fd62f15SChuanhong Guo config->addr = addr;
4054fd62f15SChuanhong Guo ret = mtk_ecc_enable(ecc, config);
4064fd62f15SChuanhong Guo if (ret) {
4074fd62f15SChuanhong Guo dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
4084fd62f15SChuanhong Guo return ret;
4094fd62f15SChuanhong Guo }
4104fd62f15SChuanhong Guo
4114fd62f15SChuanhong Guo ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
4124fd62f15SChuanhong Guo if (ret)
4134fd62f15SChuanhong Guo goto timeout;
4144fd62f15SChuanhong Guo
4154fd62f15SChuanhong Guo mtk_ecc_wait_idle(ecc, ECC_ENCODE);
4164fd62f15SChuanhong Guo
4174fd62f15SChuanhong Guo /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
4184fd62f15SChuanhong Guo len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
4194fd62f15SChuanhong Guo
4204fd62f15SChuanhong Guo /* write the parity bytes generated by the ECC back to temp buffer */
4214fd62f15SChuanhong Guo __ioread32_copy(ecc->eccdata,
4224fd62f15SChuanhong Guo ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
4234fd62f15SChuanhong Guo round_up(len, 4));
4244fd62f15SChuanhong Guo
4254fd62f15SChuanhong Guo /* copy into possibly unaligned OOB region with actual length */
4264fd62f15SChuanhong Guo memcpy(data + bytes, ecc->eccdata, len);
4274fd62f15SChuanhong Guo timeout:
4284fd62f15SChuanhong Guo
4294fd62f15SChuanhong Guo dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
4304fd62f15SChuanhong Guo mtk_ecc_disable(ecc);
4314fd62f15SChuanhong Guo
4324fd62f15SChuanhong Guo return ret;
4334fd62f15SChuanhong Guo }
4344fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_encode);
4354fd62f15SChuanhong Guo
mtk_ecc_adjust_strength(struct mtk_ecc * ecc,u32 * p)4364fd62f15SChuanhong Guo void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
4374fd62f15SChuanhong Guo {
4384fd62f15SChuanhong Guo const u8 *ecc_strength = ecc->caps->ecc_strength;
4394fd62f15SChuanhong Guo int i;
4404fd62f15SChuanhong Guo
4414fd62f15SChuanhong Guo for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
4424fd62f15SChuanhong Guo if (*p <= ecc_strength[i]) {
4434fd62f15SChuanhong Guo if (!i)
4444fd62f15SChuanhong Guo *p = ecc_strength[i];
4454fd62f15SChuanhong Guo else if (*p != ecc_strength[i])
4464fd62f15SChuanhong Guo *p = ecc_strength[i - 1];
4474fd62f15SChuanhong Guo return;
4484fd62f15SChuanhong Guo }
4494fd62f15SChuanhong Guo }
4504fd62f15SChuanhong Guo
4514fd62f15SChuanhong Guo *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
4524fd62f15SChuanhong Guo }
4534fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_adjust_strength);
4544fd62f15SChuanhong Guo
mtk_ecc_get_parity_bits(struct mtk_ecc * ecc)4554fd62f15SChuanhong Guo unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
4564fd62f15SChuanhong Guo {
4574fd62f15SChuanhong Guo return ecc->caps->parity_bits;
4584fd62f15SChuanhong Guo }
4594fd62f15SChuanhong Guo EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
4604fd62f15SChuanhong Guo
4614fd62f15SChuanhong Guo static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
462*4d21176fSXiangsheng Hou .err_mask = ECC_ERRMASK_MT2701,
463d3353719SLinus Torvalds .err_shift = 8,
4644fd62f15SChuanhong Guo .ecc_strength = ecc_strength_mt2701,
4654fd62f15SChuanhong Guo .ecc_regs = mt2701_ecc_regs,
4664fd62f15SChuanhong Guo .num_ecc_strength = 20,
4674fd62f15SChuanhong Guo .ecc_mode_shift = 5,
4684fd62f15SChuanhong Guo .parity_bits = 14,
4694fd62f15SChuanhong Guo .pg_irq_sel = 0,
4704fd62f15SChuanhong Guo };
4714fd62f15SChuanhong Guo
4724fd62f15SChuanhong Guo static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
473*4d21176fSXiangsheng Hou .err_mask = ECC_ERRMASK_MT2712,
474d3353719SLinus Torvalds .err_shift = 8,
4754fd62f15SChuanhong Guo .ecc_strength = ecc_strength_mt2712,
4764fd62f15SChuanhong Guo .ecc_regs = mt2712_ecc_regs,
4774fd62f15SChuanhong Guo .num_ecc_strength = 23,
4784fd62f15SChuanhong Guo .ecc_mode_shift = 5,
4794fd62f15SChuanhong Guo .parity_bits = 14,
4804fd62f15SChuanhong Guo .pg_irq_sel = 1,
4814fd62f15SChuanhong Guo };
4824fd62f15SChuanhong Guo
4834fd62f15SChuanhong Guo static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
484*4d21176fSXiangsheng Hou .err_mask = ECC_ERRMASK_MT7622,
485d3353719SLinus Torvalds .err_shift = 5,
4864fd62f15SChuanhong Guo .ecc_strength = ecc_strength_mt7622,
4874fd62f15SChuanhong Guo .ecc_regs = mt7622_ecc_regs,
488d3353719SLinus Torvalds .num_ecc_strength = 5,
4894fd62f15SChuanhong Guo .ecc_mode_shift = 4,
4904fd62f15SChuanhong Guo .parity_bits = 13,
4914fd62f15SChuanhong Guo .pg_irq_sel = 0,
4924fd62f15SChuanhong Guo };
4934fd62f15SChuanhong Guo
494*4d21176fSXiangsheng Hou static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 = {
495*4d21176fSXiangsheng Hou .err_mask = ECC_ERRMASK_MT7622,
496*4d21176fSXiangsheng Hou .err_shift = 8,
497*4d21176fSXiangsheng Hou .ecc_strength = ecc_strength_mt7986,
498*4d21176fSXiangsheng Hou .ecc_regs = mt2712_ecc_regs,
499*4d21176fSXiangsheng Hou .num_ecc_strength = 11,
500*4d21176fSXiangsheng Hou .ecc_mode_shift = 5,
501*4d21176fSXiangsheng Hou .parity_bits = 14,
502*4d21176fSXiangsheng Hou .pg_irq_sel = 1,
503*4d21176fSXiangsheng Hou };
504*4d21176fSXiangsheng Hou
5054fd62f15SChuanhong Guo static const struct of_device_id mtk_ecc_dt_match[] = {
5064fd62f15SChuanhong Guo {
5074fd62f15SChuanhong Guo .compatible = "mediatek,mt2701-ecc",
5084fd62f15SChuanhong Guo .data = &mtk_ecc_caps_mt2701,
5094fd62f15SChuanhong Guo }, {
5104fd62f15SChuanhong Guo .compatible = "mediatek,mt2712-ecc",
5114fd62f15SChuanhong Guo .data = &mtk_ecc_caps_mt2712,
5124fd62f15SChuanhong Guo }, {
5134fd62f15SChuanhong Guo .compatible = "mediatek,mt7622-ecc",
5144fd62f15SChuanhong Guo .data = &mtk_ecc_caps_mt7622,
515*4d21176fSXiangsheng Hou }, {
516*4d21176fSXiangsheng Hou .compatible = "mediatek,mt7986-ecc",
517*4d21176fSXiangsheng Hou .data = &mtk_ecc_caps_mt7986,
5184fd62f15SChuanhong Guo },
5194fd62f15SChuanhong Guo {},
5204fd62f15SChuanhong Guo };
5214fd62f15SChuanhong Guo
mtk_ecc_probe(struct platform_device * pdev)5224fd62f15SChuanhong Guo static int mtk_ecc_probe(struct platform_device *pdev)
5234fd62f15SChuanhong Guo {
5244fd62f15SChuanhong Guo struct device *dev = &pdev->dev;
5254fd62f15SChuanhong Guo struct mtk_ecc *ecc;
5264fd62f15SChuanhong Guo u32 max_eccdata_size;
5274fd62f15SChuanhong Guo int irq, ret;
5284fd62f15SChuanhong Guo
5294fd62f15SChuanhong Guo ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
5304fd62f15SChuanhong Guo if (!ecc)
5314fd62f15SChuanhong Guo return -ENOMEM;
5324fd62f15SChuanhong Guo
5334fd62f15SChuanhong Guo ecc->caps = of_device_get_match_data(dev);
5344fd62f15SChuanhong Guo
5354fd62f15SChuanhong Guo max_eccdata_size = ecc->caps->num_ecc_strength - 1;
5364fd62f15SChuanhong Guo max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
5374fd62f15SChuanhong Guo max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
5384fd62f15SChuanhong Guo max_eccdata_size = round_up(max_eccdata_size, 4);
5394fd62f15SChuanhong Guo ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
5404fd62f15SChuanhong Guo if (!ecc->eccdata)
5414fd62f15SChuanhong Guo return -ENOMEM;
5424fd62f15SChuanhong Guo
5434fd62f15SChuanhong Guo ecc->regs = devm_platform_ioremap_resource(pdev, 0);
5444fd62f15SChuanhong Guo if (IS_ERR(ecc->regs))
5454fd62f15SChuanhong Guo return PTR_ERR(ecc->regs);
5464fd62f15SChuanhong Guo
5474fd62f15SChuanhong Guo ecc->clk = devm_clk_get(dev, NULL);
5484fd62f15SChuanhong Guo if (IS_ERR(ecc->clk)) {
5494fd62f15SChuanhong Guo dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
5504fd62f15SChuanhong Guo return PTR_ERR(ecc->clk);
5514fd62f15SChuanhong Guo }
5524fd62f15SChuanhong Guo
5534fd62f15SChuanhong Guo irq = platform_get_irq(pdev, 0);
5544fd62f15SChuanhong Guo if (irq < 0)
5554fd62f15SChuanhong Guo return irq;
5564fd62f15SChuanhong Guo
5574fd62f15SChuanhong Guo ret = dma_set_mask(dev, DMA_BIT_MASK(32));
5584fd62f15SChuanhong Guo if (ret) {
5594fd62f15SChuanhong Guo dev_err(dev, "failed to set DMA mask\n");
5604fd62f15SChuanhong Guo return ret;
5614fd62f15SChuanhong Guo }
5624fd62f15SChuanhong Guo
5634fd62f15SChuanhong Guo ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
5644fd62f15SChuanhong Guo if (ret) {
5654fd62f15SChuanhong Guo dev_err(dev, "failed to request irq\n");
5664fd62f15SChuanhong Guo return -EINVAL;
5674fd62f15SChuanhong Guo }
5684fd62f15SChuanhong Guo
5694fd62f15SChuanhong Guo ecc->dev = dev;
5704fd62f15SChuanhong Guo mutex_init(&ecc->lock);
5714fd62f15SChuanhong Guo platform_set_drvdata(pdev, ecc);
5724fd62f15SChuanhong Guo dev_info(dev, "probed\n");
5734fd62f15SChuanhong Guo
5744fd62f15SChuanhong Guo return 0;
5754fd62f15SChuanhong Guo }
5764fd62f15SChuanhong Guo
5774fd62f15SChuanhong Guo #ifdef CONFIG_PM_SLEEP
mtk_ecc_suspend(struct device * dev)5784fd62f15SChuanhong Guo static int mtk_ecc_suspend(struct device *dev)
5794fd62f15SChuanhong Guo {
5804fd62f15SChuanhong Guo struct mtk_ecc *ecc = dev_get_drvdata(dev);
5814fd62f15SChuanhong Guo
5824fd62f15SChuanhong Guo clk_disable_unprepare(ecc->clk);
5834fd62f15SChuanhong Guo
5844fd62f15SChuanhong Guo return 0;
5854fd62f15SChuanhong Guo }
5864fd62f15SChuanhong Guo
mtk_ecc_resume(struct device * dev)5874fd62f15SChuanhong Guo static int mtk_ecc_resume(struct device *dev)
5884fd62f15SChuanhong Guo {
5894fd62f15SChuanhong Guo struct mtk_ecc *ecc = dev_get_drvdata(dev);
5904fd62f15SChuanhong Guo int ret;
5914fd62f15SChuanhong Guo
5924fd62f15SChuanhong Guo ret = clk_prepare_enable(ecc->clk);
5934fd62f15SChuanhong Guo if (ret) {
5944fd62f15SChuanhong Guo dev_err(dev, "failed to enable clk\n");
5954fd62f15SChuanhong Guo return ret;
5964fd62f15SChuanhong Guo }
5974fd62f15SChuanhong Guo
5984fd62f15SChuanhong Guo return 0;
5994fd62f15SChuanhong Guo }
6004fd62f15SChuanhong Guo
6014fd62f15SChuanhong Guo static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
6024fd62f15SChuanhong Guo #endif
6034fd62f15SChuanhong Guo
6044fd62f15SChuanhong Guo MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
6054fd62f15SChuanhong Guo
6064fd62f15SChuanhong Guo static struct platform_driver mtk_ecc_driver = {
6074fd62f15SChuanhong Guo .probe = mtk_ecc_probe,
6084fd62f15SChuanhong Guo .driver = {
6094fd62f15SChuanhong Guo .name = "mtk-ecc",
6104fd62f15SChuanhong Guo .of_match_table = mtk_ecc_dt_match,
6114fd62f15SChuanhong Guo #ifdef CONFIG_PM_SLEEP
6124fd62f15SChuanhong Guo .pm = &mtk_ecc_pm_ops,
6134fd62f15SChuanhong Guo #endif
6144fd62f15SChuanhong Guo },
6154fd62f15SChuanhong Guo };
6164fd62f15SChuanhong Guo
6174fd62f15SChuanhong Guo module_platform_driver(mtk_ecc_driver);
6184fd62f15SChuanhong Guo
6194fd62f15SChuanhong Guo MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
6204fd62f15SChuanhong Guo MODULE_DESCRIPTION("MTK Nand ECC Driver");
6214fd62f15SChuanhong Guo MODULE_LICENSE("Dual MIT/GPL");
622