| /openbmc/linux/drivers/mtd/nand/ |
| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 menu "ECC engine support"
19 bool "Software Hamming ECC engine"
31 bool "NAND ECC Smart Media byte order"
35 Software ECC according to the Smart Media Specification.
39 bool "Software BCH ECC engine"
46 ECC codes. They are used with NAND devices requiring more than 1 bit
50 bool "Macronix external hardware ECC engine"
54 This enables support for the hardware ECC engine from Macronix.
57 tristate "Mediatek hardware ECC engine"
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| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
16 * nanddev_isbad() - Check if a block is bad
35 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
50 return nand->ops->isbad(nand, pos); in nanddev_isbad()
55 * nanddev_markbad() - Mark a block as bad
60 * calls the low-level markbad hook (nand->ops->markbad()).
73 ret = nand->ops->markbad(nand, pos); in nanddev_markbad()
90 mtd->ecc_stats.badblocks++; in nanddev_markbad()
97 * nanddev_isreserved() - Check whether an eraseblock is reserved or not
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| H A D | ecc-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Macronix external hardware ECC engine for NAND devices, also
4 * called DPE for Data Processing Engine.
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
53 /* ECC Chunk Size */
63 /* ECC Chunk Count */
98 /* ECC machinery */
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic()
128 if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL) in nand_to_mxic()
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| H A D | ecc-sw-bch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
29 memset(code, 0, engine_conf->code_size); in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
33 for (i = 0; i < engine_conf->code_size; i++) in nand_ecc_sw_bch_calculate()
34 code[i] ^= engine_conf->eccmask[i]; in nand_ecc_sw_bch_calculate()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
27 A phandle on the hardware ECC engine if any. There are
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| H A D | mxicy,nand-ecc-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix NAND ECC engine
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: mxicy,nand-ecc-engine-rev3
26 - compatible
27 - reg
32 - |
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| H A D | mediatek,nand-ecc-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
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| H A D | mediatek,mtk-nfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
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| H A D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
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| H A D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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| /openbmc/linux/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_ecc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * ingenic_ecc_correct() - detect and correct bit errors
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| /openbmc/linux/include/linux/mtd/ |
| H A D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
74 * These information are usually used by specific sub-layers to select the
86 * enum nand_page_io_req_type - Direction of an I/O request
96 * struct nand_page_io_req - NAND I/O request object
107 * This object is used to pass per-page I/O requests to NAND sub-layers. This
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| H A D | nand-ecc-sw-bch.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This file is the header for the NAND BCH ECC implementation.
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
17 * engine needs
19 * @calc_buf: Buffer to use when calculating ECC bytes
20 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
23 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
51 return -ENOTSUPP; in nand_ecc_sw_bch_calculate()
59 return -ENOTSUPP; in nand_ecc_sw_bch_correct()
64 return -ENOTSUPP; in nand_ecc_sw_bch_init_ctx()
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| H A D | nand-ecc-sw-hamming.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
7 * This file is the header for the NAND Hamming ECC implementation.
16 * struct nand_ecc_sw_hamming_conf - private software Hamming ECC engine structure
18 * engine needs
20 * @calc_buf: Buffer to use when calculating ECC bytes
21 * @code_buf: Buffer to use when reading (raw) ECC bytes from the chip
52 return -ENOTSUPP; in nand_ecc_sw_hamming_init_ctx()
61 return -ENOTSUPP; in ecc_sw_hamming_calculate()
68 return -ENOTSUPP; in nand_ecc_sw_hamming_calculate()
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| /openbmc/u-boot/doc/ |
| H A D | README.nand | 1 # SPDX-License-Identifier: GPL-2.0+
32 If `clean' is specified, a JFFS2-style clean marker is written to
49 Read `size' bytes from the out-of-band data area corresponding to
51 data for one 512-byte page or 2 256-byte pages. There is no check
52 for bad blocks or ECC errors.
68 described above -- with the additional check that all pages at the end
73 [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
76 Write `size' bytes from `addr' to the out-of-band data area
78 of data for one 512-byte page or 2 256-byte pages. There is no check
84 "addr" in memory. This is a raw access, so ECC is avoided and the
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
17 in single, dual or quad IO mode with pipelined ECC encoding/decoding
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| /openbmc/openbmc/meta-security/meta-tpm/recipes-tpm2/tpm2-tss-engine/files/ |
| H A D | 0002-Fix-mismatch-of-OpenSSL-function-signatures-that-cau.patch | 5 errors with gcc-14
7 Building with gcc-14 fails with diagnostics like this:
10 src/tpm2-tss-engine-rsa.c:805:46: error: passing argument 2 of 'EVP_PKEY_meth_set_copy' from incomp…
22 Upstream-Status: Backport
24 Signed-off-by: Matthias Gerstner <matthias.gerstner@suse.de>
25 Signed-off-by: Armin Kuster <akuster808@gmail.com>
27 ---
28 src/tpm2-tss-engine-ecc.c | 4 ++--
29 src/tpm2-tss-engine-rsa.c | 4 ++--
30 2 files changed, 4 insertions(+), 4 deletions(-)
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| /openbmc/linux/drivers/crypto/intel/keembay/ |
| H A D | keembay-ocs-ecc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS ECC Crypto Driver.
5 * Copyright (C) 2019-2021 Intel Corporation
12 #include <crypto/engine.h>
13 #include <crypto/internal/ecc.h>
32 #define DRV_NAME "keembay-ocs-ecc"
52 /* ECC Instruction : for ECC_COMMAND */
76 * struct ocs_ecc_dev - ECC device context
78 * @dev: OCS ECC device
79 * @base_reg: IO base address of OCS ECC
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-sw-bch.h>
21 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
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| /openbmc/linux/include/linux/ |
| H A D | ccp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
61 * will be -EINPROGRESS. Any other "err" value during callback is
65 * the return code is -EINPROGRESS or
66 * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 9 This option, if enabled, provides more flexible and linux-like
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
88 of OOB area before last ECC sector data starts. This is potentially
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| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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| /openbmc/u-boot/include/ |
| H A D | fsl_fman.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
77 u32 fmbm_rfne; /* Rx frame next engine */
79 u32 fmbm_rfpne; /* Rx frame parser next engine */
89 u32 fmbm_rfene; /* Rx frame enqueue next engine */
119 /* FMBM_RCFG - Rx configuration */
124 /* FMBM_RST - Rx status */
127 /* FMBM_RFCA - Rx frame command attributes */
132 /* FMBM_RSTC - Rx statistics */
142 u32 fmbm_tfne; /* Tx frame next engine */
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