Home
last modified time | relevance | path

Searched +full:double +full:- +full:speed +full:- +full:clock (Results 1 – 25 of 156) sorted by relevance

1234567

/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DDimm.interface.yaml4 - name: MemoryDataWidth
8 - name: MemorySizeInKB
12 - name: MemoryDeviceLocator
16 - name: MemoryType
20 - name: MemoryTypeDetail
24 - name: MaxMemorySpeedInMhz
27 The maximum capable clock speed of Memory, in megahertz.
28 - name: MemoryAttributes
33 - name: MemoryConfiguredSpeedInMhz
36 Configured clock speed to Memory, in megahertz.
[all …]
/openbmc/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DProcessor.v1_20_1.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
34 "description": "The available OEM-specific actions for this resource.",
35 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
47 "Disabled": "Base speed priority is disabled.",
48 "Enabled": "Base speed priority is enabled."
57 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
82 "description": "The maximum speed supported by this interface.",
83 … "longDescription": "This property shall contain the maximum speed supported by this interface.",
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DProcessor.v1_20_1.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
34 "description": "The available OEM-specific actions for this resource.",
35 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
47 "Disabled": "Base speed priority is disabled.",
48 "Enabled": "Base speed priority is enabled."
57 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
82 "description": "The maximum speed supported by this interface.",
83 … "longDescription": "This property shall contain the maximum speed supported by this interface.",
[all …]
/openbmc/linux/sound/pci/echoaudio/
H A Dechoaudio.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
[all …]
H A Dechoaudio_dsp.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
81 * These are the offsets for the memory-mapped DSP registers; the DSP base
133 #define MIDI_IN_SKIP_DATA (-1)
136 /*----------------------------------------------------------------------------
147 50 to 100 kHz inclusive for double speed mode.
151 -Set the clock select bits in the control register to 0xe (see the #define
[all …]
H A Dmona_dsp.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
45 return -ENODEV; in init_hw()
49 dev_err(chip->card->dev, in init_hw()
50 "init_hw - could not initialize DSP comm page\n"); in init_hw()
54 chip->device_id = device_id; in init_hw()
55 chip->subdevice_id = subdevice_id; in init_hw()
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
27 * @pclk: peripheral clock for the IDE block
48 /* Gemini-specific properties */
93 * The unit of the below required timings is two clock periods of the ATA
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
142 struct ftide010 *ftide = ap->host->private_data; in ftide010_set_dmamode()
143 u8 speed = adev->dma_mode; in ftide010_set_dmamode() local
144 u8 devno = adev->devno & 1; in ftide010_set_dmamode()
[all …]
H A Dpata_opti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_opti.c - ATI PATA for new ATA layer
9 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
47 * opti_pre_reset - probe begin
56 struct ata_port *ap = link->ap; in opti_pre_reset()
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in opti_pre_reset()
63 if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no])) in opti_pre_reset()
64 return -ENOENT; in opti_pre_reset()
70 * opti_write_reg - control register setup
76 * rather than using PCI space as other controllers do. The double inw
[all …]
/openbmc/phosphor-fan-presence/monitor/
H A Dtach_sensor.hpp3 #include <phosphor-logging/log.hpp>
6 #include <sdeventplus/clock.hpp>
29 * - init - only do the initialization steps
30 * - monitor - run normal monitoring algorithm
40 * - func - Transition to functional state timer
41 * - nonfunc - Transition to nonfunctional state timer
51 * - time - Use a percentage based deviation
52 * - count - Run up/down count fault detection
65 * set a speed. Since it doesn't necessarily have a Target, it
87 * @param[in] mode - mode of fan monitor
[all …]
/openbmc/u-boot/drivers/i2c/
H A Di2c-uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2015-2016 Socionext Inc.
28 u32 clk; /* clock frequency control */
43 unsigned long input_clk; /* master clock (Hz) */
54 return -EINVAL; in uniphier_i2c_probe()
56 priv->regs = devm_ioremap(dev, addr, SZ_64); in uniphier_i2c_probe()
57 if (!priv->regs) in uniphier_i2c_probe()
58 return -ENOMEM; in uniphier_i2c_probe()
60 priv->input_clk = IOBUS_FREQ; in uniphier_i2c_probe()
62 priv->dev = dev; in uniphier_i2c_probe()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
/openbmc/linux/sound/soc/codecs/
H A Des7241.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
39 gpiod_set_value_cansleep(priv->reset, 0); in es7241_set_mode()
42 gpiod_set_value_cansleep(priv->m0, m0); in es7241_set_mode()
43 gpiod_set_value_cansleep(priv->m1, m1); in es7241_set_mode()
45 /* take the device out of reset - datasheet does not specify a delay */ in es7241_set_mode()
46 gpiod_set_value_cansleep(priv->reset, 1); in es7241_set_mode()
58 for (j = 0; j < mode->slv_mfs_num; j++) { in es7241_set_consumer_mode()
59 if (mode->slv_mfs[j] == mfs) in es7241_set_consumer_mode()
63 return -EINVAL; in es7241_set_consumer_mode()
75 * We can't really set clock ratio, if the mclk/lrclk is different in es7241_set_provider_mode()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
[all …]
/openbmc/linux/tools/spi/
H A Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
43 static uint32_t speed = 500000; variable
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
127 .speed_hz = speed, in transfer()
175 printf("Usage: %s [-2348CDFHILMNORSZbdilopsv]\n", prog); in print_usage()
177 " -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
178 " -s --speed max speed (Hz)\n" in print_usage()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Duninorth.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * Uni-N and U3 config space reg. definitions
58 * This word contains, in little-endian format (!!!), the physical address
78 * Turning on AGP seem to require a double invalidate operation, one before
92 * Uni-N memory mapped reg. definitions
94 * Those registers are Big-Endian !!
114 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
115 #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
116 #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
117 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
[all …]
/openbmc/linux/Documentation/powerpc/
H A Ddawr-power9.rst18 clock : 3800.000000MHz
62 speed since it can use the hardware emulation. Unfortunately if this
97 To double check the DAWR is working, run this kernel selftest:
99 tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c
/openbmc/linux/drivers/usb/renesas_usbhs/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
114 #define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */
[all …]
/openbmc/linux/drivers/usb/dwc2/
H A Dcore.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
37 dev_name(hsotg->dev), ##__VA_ARGS__)
42 /* dwc2-hsotg declarations */
74 * struct dwc2_hsotg_ep - driver endpoint definition.
[all …]
/openbmc/linux/drivers/net/wan/
H A Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
24 * speed frame shifter mode. This is sometimes referred to as X.21 mode
30 * purpose (FarSite T-series).
104 unsigned char internalClock; /* 1 => internal clock, 0 => external */
105 unsigned int lineSpeed; /* Speed in bps */
113 unsigned char invertClock; /* Invert clock feature for syncing */
117 unsigned char structure; /* unframed, double, crc4, f4, f12, */
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
[all …]
/openbmc/linux/Documentation/driver-api/i3c/
H A Dprotocol.rst1 .. SPDX-License-Identifier: GPL-2.0
17 https://resources.mipi.org/mipi-i3c-v1-download).
22 The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
23 to overcome I2C limitations (limited speed, external signals needed for
25 while remaining power-efficient.
42 I3C is a multi-master protocol, so there might be several masters on a bus,
51 In addition to these per-device addresses, the protocol defines a broadcast
70 * BCR: Bus Characteristic Register. This 8-bit register describes the device bus
72 * DCR: Device Characteristic Register. This 8-bit register describes the
74 * Provisional ID: A 48-bit unique identifier. On a given bus there should be no
[all …]
/openbmc/linux/Documentation/networking/dsa/
H A Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
[all …]
/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
21 /* TX-Port: Unsupported Format */
29 /* IPR non-consistent-sp */
66 /* non Frame-Manager error */
101 FMAN_EX_FPM_DOUBLE_ECC, /* Double ECC error on FPM ram access */
103 FMAN_EX_QMI_DOUBLE_ECC, /* Double bit ECC occurred on QMI */
109 FMAN_EX_IRAM_ECC, /* Double bit ECC occurred on IRAM */
110 FMAN_EX_MURAM_ECC /* Double bit ECC occurred on MURAM */
122 __be16 cksum; /* Running-sum */
[all …]
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
31 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
36 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
40 * cclkin: source clock of mmc controller in dw_mci_rk3288_set_ios()
41 * bus_hz: card interface clock generated by CLKGEN in dw_mci_rk3288_set_ios()
43 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
48 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
[all …]

1234567