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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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/openbmc/phosphor-power/phosphor-regulators/src/actions/
H A Daction_environment.hpp8 * http://www.apache.org/licenses/LICENSE-2.0
42 * - current device ID
43 * - current volts value (if any)
44 * - mapping from device and rule IDs to the corresponding objects
45 * - rule call stack depth (to detect infinite recursion)
46 * - reference to system services
47 * - faults detected by actions (if any)
48 * - additional error data captured by actions (if any)
53 // Specify which compiler-generated methods we want
95 * Adds the specified phase fault to the set of faults that have been
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/openbmc/qemu/hw/audio/
H A Dfmopl.h5 typedef void (*OPL_TIMERHANDLER)(void *param, int channel, double interval_Sec);
10 /* ---------- OPL one of slot ---------- */
26 uint8_t evm; /* envelope phase */
40 /* ---------- OPL one of channel ---------- */
48 /* phase generator state */
60 double freqbase; /* frequency base */
61 double TimerBase; /* Timer base time (==sampling time) */
77 uint32_t FN_TABLE[1024]; /* fnumber -> increment counter */
92 /* ---------- Generic interface section ---------- */
H A Dfmopl.c3 ** File: fmopl.c -- software implementation of FM sound generator
41 /* -------------------- for debug --------------------- */
49 /* -------------------- preliminary define section --------------------- */
54 #define DELTAT_MIXING_LEVEL (1) /* DELTA-T ADPCM MIXING LEVEL */
59 #define FREQ_RATE (1<<(FREQ_BITS-20))
63 #define OPL_OUTSB (TL_BITS+3-16) /* OPL output final shift 16bit */
65 #define OPL_MINOUT (-0x8000<<OPL_OUTSB)
67 /* -------------------- quality selection --------------------- */
91 #define VIB_SHIFT (32-9)
93 #define AMS_SHIFT (32-9)
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
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H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
182 double vtotal_avg) in optc3_fpu_set_vrr_m_const()
185 double vtotal_min, vtotal_max; in optc3_fpu_set_vrr_m_const()
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const() local
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
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/openbmc/linux/drivers/ptp/
H A Dptp_idt82p33.h1 /* SPDX-License-Identifier: GPL-2.0+ */
46 * @brief Maximum absolute value for write phase offset in nanoseconds
50 /** @brief Phase offset resolution
52 * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
64 /* Workaround for TOD-to-output alignment issue */
67 /* double dco mode */
/openbmc/phosphor-power/phosphor-regulators/test/
H A Ddevice_tests.cpp8 * http://www.apache.org/licenses/LICENSE-2.0
71 this->chassis = chassis.get();
77 this->system =
124 std::optional<double> volts{}; in TEST_F()
158 EXPECT_EQ(device.getPresenceDetection()->getActions().size(), 1); in TEST_F()
160 EXPECT_EQ(device.getConfiguration()->getVolts().has_value(), false); in TEST_F()
161 EXPECT_EQ(device.getConfiguration()->getActions().size(), 2); in TEST_F()
163 EXPECT_EQ(device.getPhaseFaultDetection()->getActions().size(), 3); in TEST_F()
231 presenceDetectionPtr->execute(services, *system, *chassis, device); in TEST_F()
232 EXPECT_TRUE(presenceDetectionPtr->getCachedPresence().has_value()); in TEST_F()
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32- bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max.
16 - Pulse input 3 lines
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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
31 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
36 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
43 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
48 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
49 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
50 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
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H A Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
137 /* Max load for eMMC Vdd-io supply */
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
300 return msm_host->offset; in sdhci_priv_msm_offset()
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/openbmc/linux/drivers/block/
H A Dswim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * 2004-08-21 (lv) - Initial implementation
12 * 2008-10-30 (lv) - Port to 2.6
18 #include <linux/blk-mq.h>
39 #define DRIVER_VERSION "Version 0.2 (2008-10-30)"
41 #define REG(x) unsigned char x, x ## _pad[0x200 - 1];
63 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v))
64 #define swim_read(base, reg) in_8(&(base)->read_##reg)
87 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v))
88 #define iwm_read(base, reg) in_8(&(base)->reg)
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/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
25 * to get a "phase" and get 1 decimal point precision.
29 #define SJA1105_RGMII_DELAY_PHASE_TO_PS(phase) \ argument
30 ((800 * (phase)) / 360)
31 #define SJA1105_RGMII_DELAY_PHASE_TO_HW(phase) \ argument
32 (((phase) - 738) / 9)
124 * 64-bit values back.
271 /* PTP two-step TX timestamp ID, and its serialization lock */
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1 // SPDX-License-Identifier: GPL-2.0
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
60 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
77 * Phase 1: Load pattern (using ODPG) in ddr3_tip_dynamic_read_leveling()
81 * assuming non multi-CS configuration in ddr3_tip_dynamic_read_leveling()
103 * Phase 2: ODPG to Read Leveling mode in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
121 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
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/openbmc/qemu/migration/
H A Dmigration.h10 * the COPYING file in the top-level directory.
17 #include "exec/cpu-common.h"
18 #include "hw/qdev-core.h"
19 #include "qapi/qapi-types-migration.h"
20 #include "qapi/qmp/json-writer.h"
24 #include "io/channel-buffer.h"
27 #include "postcopy-ram.h"
50 * 1<<6=64 pages -> 256K chunk when page size is 4K. This gives us
56 * 1<<18=256K pages -> 1G chunk when page size is 4K. This is the
61 * 1<<31=2G pages -> 8T chunk when page size is 4K. This should be
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/openbmc/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
105 * we simply use double precision math, in order to avoid the in ppb_to_scaled_ppm()
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
124 " -g get the ptp clock time\n" in usage()
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
79 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
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/openbmc/openbmc/poky/meta/recipes-connectivity/wpa-supplicant/wpa-supplicant/
H A Dwpa_supplicant.conf48 # run as non-root users. However, since the control interface can be used to
51 # want to allow non-root users to use the control interface, add a new group
69 # library/default.asp?url=/library/en-us/secauthz/security/
72 # DACL (which will reject all connections). See README-Windows.txt for more
78 # wpa_supplicant is implemented based on IEEE Std 802.1X-2004 which defines
95 # non-WPA drivers when using IEEE 802.1X mode; do not try to associate with
107 # EAP fast re-authentication
108 # By default, fast re-authentication is enabled for all EAP methods that
109 # support it. This variable can be used to disable fast re-authentication.
123 #pkcs11_module_path=/usr/lib/pkcs11/opensc-pkcs11.so
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/openbmc/linux/arch/parisc/math-emu/
H A Dfmpyfadd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
15 * Double Floating-point Multiply Fused Add
16 * Double Floating-point Multiply Negate Fused Add
17 * Single Floating-point Multiply Fused Add
18 * Single Floating-point Multiply Negate Fused Add
41 * Double Floating-point Multiply Fused Add
77 mpy_exponent = Dbl_exponent(opnd1p1) + Dbl_exponent(opnd2p1) - DBL_BIAS; in dbl_fmpyfadd()
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H A Ddfsub.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
15 * Double_subtract: subtract two double precision values.
33 * Double_subtract: subtract two double precision values.
266 diff_exponent = result_exponent - right_exponent; in dbl_fsub()
289 * normalization phase. in dbl_fsub()
313 /* Must have been "x-x" or "x+(-x)". */ in dbl_fsub()
319 result_exponent--; in dbl_fsub()
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/openbmc/fb-ipmi-oem/src/
H A Dusb-dbg.cpp2 * Copyright (c) 2018-present Facebook. All Rights Reserved.
8 * http://www.apache.org/licenses/LICENSE-2.0
18 #include <usb-dbg.hpp>
42 int getSensorValue(std::string&, double&);
70 lg2::error("Unable to get max host position - {MAXPOSITION}", in getMaxHostPosition()
89 lg2::error("Unable to get host position - {POSITION}", "POSITION", in getSelectorPosition()
95 static int panelNum = (sizeof(panels) / sizeof(struct ctrl_panel)) - 1;
97 /* Returns the FRU the hand-switch is switched to. If it is switched to BMC
160 lines--; in append()
192 return -1; in getPage()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c44 link->ctx->logger
69 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
98 * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
109 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
111 link->link_id.enum_id - ENUM_ID_1, in dpia_configure_link()
112 lt_settings->lttpr_mode); in dpia_configure_link()
119 dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode); in dpia_configure_link()
122 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
127 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
132 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
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/openbmc/linux/tools/perf/Documentation/
H A Dperf-c2c.txt1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] \-- [<record command options>] <command>
16 -----------
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
32 - memory address of the access
33 - type of the access (load and store details)
34 - latency (in cycles) of the load access
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/openbmc/linux/drivers/scsi/
H A Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
96 u8 phase; member
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