Lines Matching +full:double +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
60 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
77 * Phase 1: Load pattern (using ODPG) in ddr3_tip_dynamic_read_leveling()
81 * assuming non multi-CS configuration in ddr3_tip_dynamic_read_leveling()
103 * Phase 2: ODPG to Read Leveling mode in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
121 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
136 * Phase 2: Mask config in ddr3_tip_dynamic_read_leveling()
142 * Phase 3: Read Leveling execution in ddr3_tip_dynamic_read_leveling()
198 /* double loop on bus, pup */ in ddr3_tip_dynamic_read_leveling()
199 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
200 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
206 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling()
241 * Phase 3: Exit Read Leveling in ddr3_tip_dynamic_read_leveling()
266 /* double loop on bus, pup */ in ddr3_tip_dynamic_read_leveling()
267 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
268 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
272 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling()
290 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
291 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
303 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
304 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
324 * cs_mask = 0x1 <<20 Trn_CS0 - CS0 is included in the DDR3 training in ddr3_tip_legacy_dynamic_write_leveling()
325 * cs_mask = 0x1 <<21 Trn_CS1 - CS1 is included in the DDR3 training in ddr3_tip_legacy_dynamic_write_leveling()
326 * cs_mask = 0x1 <<22 Trn_CS2 - CS2 is included in the DDR3 training in ddr3_tip_legacy_dynamic_write_leveling()
327 * cs_mask = 0x1 <<23 Trn_CS3 - CS3 is included in the DDR3 training in ddr3_tip_legacy_dynamic_write_leveling()
334 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_legacy_dynamic_write_leveling()
365 * cs_mask = 0x1 <<20 Trn_CS0 - CS0 is included in the DDR3 training in ddr3_tip_legacy_dynamic_read_leveling()
366 * cs_mask = 0x1 <<21 Trn_CS1 - CS1 is included in the DDR3 training in ddr3_tip_legacy_dynamic_read_leveling()
367 * cs_mask = 0x1 <<22 Trn_CS2 - CS2 is included in the DDR3 training in ddr3_tip_legacy_dynamic_read_leveling()
368 * cs_mask = 0x1 <<23 Trn_CS3 - CS3 is included in the DDR3 training in ddr3_tip_legacy_dynamic_read_leveling()
380 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_legacy_dynamic_read_leveling()
402 int adll_array[3] = { 0, -0xa, 0x14 }; in ddr3_tip_dynamic_per_bit_read_leveling()
417 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
420 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
433 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
434 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
451 * Phase 1: Load pattern (using ODPG) in ddr3_tip_dynamic_per_bit_read_leveling()
455 * assuming non multi-CS configuration in ddr3_tip_dynamic_per_bit_read_leveling()
477 * Phase 2: ODPG to Read Leveling mode in ddr3_tip_dynamic_per_bit_read_leveling()
490 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
491 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
493 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_per_bit_read_leveling()
508 * Phase 2: Mask config in ddr3_tip_dynamic_per_bit_read_leveling()
514 * Phase 3: Read Leveling execution in ddr3_tip_dynamic_per_bit_read_leveling()
570 /* double loop on bus, pup */ in ddr3_tip_dynamic_per_bit_read_leveling()
571 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
572 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
577 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
645 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; in ddr3_tip_dynamic_per_bit_read_leveling()
647 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
651 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, in ddr3_tip_dynamic_per_bit_read_leveling()
679 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
680 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
683 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling()
699 * cs_bitmask = tm->interface_params[if_id]. in ddr3_tip_dynamic_per_bit_read_leveling()
704 * TBD BC2 - what is the PHY address for other in ddr3_tip_dynamic_per_bit_read_leveling()
709 * - max delay that is less than threshold in ddr3_tip_dynamic_per_bit_read_leveling()
720 * Phase 3: Exit Read Leveling in ddr3_tip_dynamic_per_bit_read_leveling()
742 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
743 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
755 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
756 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_per_bit_read_leveling()
784 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_calc_cs_mask()
786 all_bus_cs |= tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
788 same_bus_cs &= tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
792 *cs_mask &= ~tm->interface_params[if_id]. in ddr3_tip_calc_cs_mask()
814 u32 test_res = 0; /* 0 - success for all pup */ in ddr3_tip_dynamic_write_leveling()
823 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
824 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
845 /* Enable multi-CS */ in ddr3_tip_dynamic_write_leveling()
852 * Phase 1: DRAM 2 Write Leveling mode in ddr3_tip_dynamic_write_leveling()
857 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
858 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
866 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
867 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
877 /*enable write leveling to all cs - Q off , WL n */ in ddr3_tip_dynamic_write_leveling()
882 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
883 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
890 /* Enable Output buffer to relevant CS - Q on , WL on */ in ddr3_tip_dynamic_write_leveling()
905 * Phase 2: Set training IP to write leveling mode in ddr3_tip_dynamic_write_leveling()
910 /* phase 3: trigger training */ in ddr3_tip_dynamic_write_leveling()
919 if (tm->bus_act_mask == 0xb) /* set to data to 0 to skip the check */ in ddr3_tip_dynamic_write_leveling()
927 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
949 * Phase 3.5: Validate result in ddr3_tip_dynamic_write_leveling()
952 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
954 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
957 * "16" below is for a half-phase in ddr3_tip_dynamic_write_leveling()
961 * Write to WL register: ADLL [4:0], Phase [8:6], in ddr3_tip_dynamic_write_leveling()
1000 * Phase 4: Exit write leveling mode in ddr3_tip_dynamic_write_leveling()
1018 /* Update MRS 1 (return to functional mode - Q on , WL off) */ in ddr3_tip_dynamic_write_leveling()
1034 * Phase 5: Load WL values to each PHY in ddr3_tip_dynamic_write_leveling()
1038 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1039 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1044 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
1059 * ([4:0] ADLL, [8:6] Phase, [15:10] in ddr3_tip_dynamic_write_leveling()
1068 * in case phase remove should be executed in ddr3_tip_dynamic_write_leveling()
1069 * need to remove more than one phase. in ddr3_tip_dynamic_write_leveling()
1071 * where there could be more than one phase between sub-phys in ddr3_tip_dynamic_write_leveling()
1124 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1125 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1148 /* Disable modt0 for CS0 training - need to adjust for multi-CS in ddr3_tip_dynamic_write_leveling()
1162 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling()
1163 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling()
1182 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling_supp()
1183 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling_supp()
1187 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_write_leveling_supp()
1234 adll_offset = -5; in ddr3_tip_dynamic_write_leveling_supp()
1275 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_write_leveling_supp()
1276 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_write_leveling_supp()
1285 * Phase Shift
1298 /* Read current phase */ in ddr3_tip_wl_supp_align_phase_shift()
1304 /* Set phase (0x0[6-8]) -2 */ in ddr3_tip_wl_supp_align_phase_shift()
1310 ((original_phase - 2) << 6); in ddr3_tip_wl_supp_align_phase_shift()
1315 (dev_num, if_id, bus_id, -2) == MV_OK) in ddr3_tip_wl_supp_align_phase_shift()
1319 /* Set phase (0x0[6-8]) +2 */ in ddr3_tip_wl_supp_align_phase_shift()
1331 /* Set phase (0x0[6-8]) +4 */ in ddr3_tip_wl_supp_align_phase_shift()
1343 /* Set phase (0x0[6-8]) +6 */ in ddr3_tip_wl_supp_align_phase_shift()
1378 num_of_word_mult = (tm->bus_act_mask == 3) ? 1 : 2; in ddr3_tip_xsb_compare_test()
1397 ("XSB-compt CS#%d: IF %d bus_id %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", in ddr3_tip_xsb_compare_test()
1410 if ((word_offset > (TEST_PATTERN_LENGTH * 2 - 1))) in ddr3_tip_xsb_compare_test()
1419 if ((TEST_PATTERN_LENGTH * num_of_word_mult - start_xsb_offset) == in ddr3_tip_xsb_compare_test()
1431 ("XSB-compt CS#%d: IF %d bus_id %d num_of_succ_byte_compare %d - Fail!\n", in ddr3_tip_xsb_compare_test()
1436 ("XSB-compt: expected 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", in ddr3_tip_xsb_compare_test()
1447 ("XSB-compt: recieved 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", in ddr3_tip_xsb_compare_test()
1511 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_write_leveling_seq()
1553 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_read_leveling_seq()
1591 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, dq_id / 8); in ddr3_tip_dynamic_per_bit_read_leveling_seq()
1611 ("I/F0 PUP0 Result[0 - success, 1-fail] ...\n")); in ddr3_tip_print_wl_supp_result()
1613 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_wl_supp_result()
1614 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_print_wl_supp_result()
1617 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_wl_supp_result()
1625 ("I/F0 PUP0 Stage[0-phase_shift, 1-clock_shift, 2-align_shift] ...\n")); in ddr3_tip_print_wl_supp_result()
1627 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_wl_supp_result()
1628 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_print_wl_supp_result()
1631 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_wl_supp_result()
1678 int cl_val = tm->interface_params[0].cas_l; in mv_ddr_rl_dqs_burst()
1719 if (IS_BUS_ACTIVE(tm->bus_act_mask, subphy_id) == 0) in mv_ddr_rl_dqs_burst()
1725 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in mv_ddr_rl_dqs_burst()
1777 if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask)) in mv_ddr_rl_dqs_burst()
1827 if ((rl_max_values[effective_cs][subphy_id][if_id] - in mv_ddr_rl_dqs_burst()
1849 if ((i - rl_values[effective_cs][subphy_id][if_id]) < in mv_ddr_rl_dqs_burst()
1888 } /* for-loop on i */ in mv_ddr_rl_dqs_burst()
1895 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_id); in mv_ddr_rl_dqs_burst()
1903 } /* for-loop on effective_cs */ in mv_ddr_rl_dqs_burst()
1905 /* post-processing read leveling results */ in mv_ddr_rl_dqs_burst()
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1925 ("%s: cs %d, min phase %d, max phase %d, read sample %d\n", in mv_ddr_rl_dqs_burst()
1929 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_id); in mv_ddr_rl_dqs_burst()
1930 /* reduce sdr cycle per cs; extract rl adll and phase values */ in mv_ddr_rl_dqs_burst()
1931 i = rl_values[effective_cs][subphy_id][if_id] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE); in mv_ddr_rl_dqs_burst()
1934 rl_phase_val -= phase_delta; in mv_ddr_rl_dqs_burst()
1945 } /* for-loop on effective cs */ in mv_ddr_rl_dqs_burst()
1948 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in mv_ddr_rl_dqs_burst()