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/openbmc/linux/kernel/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 default y
83 # Select this option if the architecture assumes DMA devices are coherent
84 # by default.
94 bool "Dynamic allocation of DMA bounce buffers"
95 default n
100 pools as needed. To reduce run-time kernel memory requirements, you
111 bool "DMA Restricted Pool"
114 This enables support for restricted DMA pools which provide a level of
115 DMA memory protection on systems with limited hardware protection
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/openbmc/linux/arch/sh/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 menu "DMA support"
6 bool "SuperH on-chip DMA controller (DMAC) support"
8 default n
13 default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \
21 bool "SuperH DMA API support"
22 default n
24 SH_DMA_API always enabled DMA API of used SuperH.
25 If you want to use DMA ENGINE, you must not enable this.
31 default "4" if CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 || \
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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H A Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
16 channels. Each channel has 2 interrupts. One is for DMA done and
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/openbmc/linux/Documentation/devicetree/bindings/reserved-memory/
H A Dshared-dma-pool.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory DMA pool
10 - devicetree-spec@vger.kernel.org
13 - $ref: reserved-memory.yaml
18 - const: shared-dma-pool
21 pool of DMA buffers for a set of devices. It can be used by an
25 - const: restricted-dma-pool
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/openbmc/linux/drivers/dma-buf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 default n
18 Documentation/driver-api/sync_file.rst.
22 default n
35 default n
39 A driver to let userspace turn memfd regions into dma-bufs.
44 default n
47 Don't pin buffers if the dynamic DMA-buf interface is available on
50 through DMA-buf.
55 bool "DMA-BUF debug checks"
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/openbmc/linux/drivers/iommu/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 bool "Support for Intel IOMMU using DMA Remapping Devices"
25 DMA remapping (DMAR) devices support enables independent address
26 translations for Direct Memory Access (DMA) from devices.
27 These DMA remapping devices are reported via ACPI tables
28 and include PCI device scope covered by these DMA
45 This option is -NOT- intended for production environments, and should
55 to access DMA resources through process address space by
59 bool "Enable Intel DMA Remapping Devices by default"
60 default y
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/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox3_common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
12 /dts-v1/;
14 #include "sama5d2-pinfunc.h"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mfd/atmel-flexcom.h>
17 #include <dt-bindings/pinctrl/at91.h>
18 #include <dt-bindings/pwm/pwm.h>
36 stdout-path = "serial1:115200n8";
41 clock-frequency = <32768>;
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H A Dat91-sama5d27_wlsom1_ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
9 /dts-v1/;
10 #include "at91-sama5d27_wlsom1.dtsi"
11 #include <dt-bindings/input/input.h>
15 …compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel…
26 stdout-path = "serial0:115200n8";
29 gpio-keys {
30 compatible = "gpio-keys";
32 pinctrl-names = "default";
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H A Dat91-wb50n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
17 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <12000000>;
46 atmel,osc-bypass;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
52 cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
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/openbmc/linux/drivers/net/wireless/broadcom/b43legacy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Broadcom 43xx-legacy wireless support (mac80211 stack)"
18 b43-fwcutter.
23 # Auto-select SSB PCI-HOST support, if possible
29 default y
31 # Auto-select SSB PCICORE driver, if possible
36 default y
44 default y
46 # This config option automatically enables b43 HW-RNG support,
47 # if the HW-RNG core is enabled.
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 compatible = "ti,j784s4-evm", "ti,j784s4";
19 stdout-path = "serial2:115200n8";
39 reserved_memory: reserved-memory {
40 #address-cells = <2>;
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H A Dk3-j721e-beagleboneai64.dts1 // SPDX-License-Identifier: GPL-2.0
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
16 #include <dt-bindings/phy/phy-cadence.h>
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H A Dk3-j721e-sk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
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H A Dk3-j721e-som-p0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
20 reserved_memory: reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
28 no-map;
31 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
32 compatible = "shared-dma-pool";
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/openbmc/linux/Documentation/driver-api/rapidio/
H A Dtsi721.rst2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
35 Its default value is 128.
37 - 'dma_txqueue_sz'
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/openbmc/linux/drivers/dma/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
20 default y
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
27 tristate "Texas Instruments sDMA (omap-dma) support"
32 default y
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
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/openbmc/linux/include/drm/
H A Ddrm_gem_dma_helper.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct drm_gem_dma_object - GEM object backed by DMA memory allocations
14 * @dma_addr: DMA address of the backing memory
17 * DMA addresses.
19 * @map_noncoherent: if true, the GEM object is backed by non-coherent memory
26 /* For objects with DMA memory allocated by GEM DMA */
52 * drm_gem_dma_object_free - GEM object function for drm_gem_dma_free()
55 * This function wraps drm_gem_dma_free_object(). Drivers that employ the DMA helpers
66 * drm_gem_dma_object_print_info() - Print &drm_gem_dma_object info for debugfs
71 * This function wraps drm_gem_dma_print_info(). Drivers that employ the DMA helpers
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/openbmc/linux/Documentation/core-api/
H A Ddma-attributes.rst2 DMA attributes
5 This document describes the semantics of the DMA attributes that are
6 defined in linux/dma-mapping.h.
9 ----------------------
15 those that do not will simply ignore the attribute and exhibit default
19 ----------------------
25 those that do not will simply ignore the attribute and exhibit default
29 --------------------------
33 such mapping is non-trivial task and consumes very limited resources
34 (like kernel virtual address space or dma consistent address space).
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dkx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/mfd/st,stpmic1.h>
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
28 compatible = "shared-dma-pool";
30 no-map;
34 compatible = "shared-dma-pool";
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H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
31 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
37 compatible = "shared-dma-pool";
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/openbmc/linux/drivers/usb/musb/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # USB Dual Role (OTG-ready) Controller Drivers
7 # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
27 module will be called "musb-hdrc".
33 default USB_MUSB_DUAL_ROLE if (USB && USB_GADGET)
34 default USB_MUSB_HOST if (USB && !USB_GADGET)
35 default USB_MUSB_GADGET if (!USB && USB_GADGET)
57 This is the default mode of working of MUSB controller where
74 tristate "DA8xx/OMAP-L1x"
125 comment "MUSB DMA mode"
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dpl011.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: serial.yaml#
22 - arm,pl011
24 - compatible
29 - const: arm,pl011
30 - const: arm,primecell
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/openbmc/qemu/hw/ppc/
H A Dppc440_uc.c5 * Copyright (c) 2016-2019 BALATON Zoltan
17 #include "hw/pci-host/ppc4xx.h"
18 #include "hw/qdev-properties.h"
40 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
91 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; in dcr_read_l2sram()
105 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; in dcr_read_l2sram()
108 default: in dcr_read_l2sram()
129 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
143 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
154 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dti-omap-hsmmc.txt10 --------------------
11 - compatible:
12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
20 ---------------------------------
22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
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