Lines Matching +full:dma +full:- +full:default
5 * Copyright (c) 2016-2019 BALATON Zoltan
17 #include "hw/pci-host/ppc4xx.h"
18 #include "hw/qdev-properties.h"
40 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
91 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; in dcr_read_l2sram()
105 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; in dcr_read_l2sram()
108 default: in dcr_read_l2sram()
129 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
143 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
154 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
163 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); in l2sram_reset()
164 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; in l2sram_reset()
165 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); in l2sram_reset()
173 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ in ppc4xx_l2sram_init()
174 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", in ppc4xx_l2sram_init()
176 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", in ppc4xx_l2sram_init()
178 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", in ppc4xx_l2sram_init()
180 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", in ppc4xx_l2sram_init()
245 ret = cpr->addr; in dcr_read_cpr()
248 switch (cpr->addr) { in dcr_read_cpr()
262 default: in dcr_read_cpr()
266 default: in dcr_read_cpr()
279 cpr->addr = val; in dcr_write_cpr()
283 default: in dcr_write_cpr()
292 cpr->addr = 0; in ppc4xx_cpr_reset()
343 ret = sdr->addr; in dcr_read_sdr()
346 switch (sdr->addr) { in dcr_read_sdr()
375 default: in dcr_read_sdr()
379 default: in dcr_read_sdr()
392 sdr->addr = val; in dcr_write_sdr()
395 switch (sdr->addr) { in dcr_write_sdr()
398 default: in dcr_write_sdr()
402 default: in dcr_write_sdr()
411 sdr->addr = 0; in sdr_reset()
453 ret = ahb->top; in dcr_read_ahb()
456 ret = ahb->bot; in dcr_read_ahb()
458 default: in dcr_read_ahb()
471 ahb->top = val; in dcr_write_ahb()
474 ahb->bot = val; in dcr_write_ahb()
484 ahb->top = 0; in ppc4xx_ahb_reset()
485 ahb->bot = 0; in ppc4xx_ahb_reset()
499 /* DMA controller */
539 PPC4xxDmaState *dma = opaque; in dcr_read_dma() local
541 int addr = dcrn - dma->base; in dcr_read_dma()
548 val = dma->ch[chnl].cr; in dcr_read_dma()
551 val = dma->ch[chnl].ct; in dcr_read_dma()
554 val = dma->ch[chnl].sa >> 32; in dcr_read_dma()
557 val = dma->ch[chnl].sa; in dcr_read_dma()
560 val = dma->ch[chnl].da >> 32; in dcr_read_dma()
563 val = dma->ch[chnl].da; in dcr_read_dma()
566 val = dma->ch[chnl].sg >> 32; in dcr_read_dma()
569 val = dma->ch[chnl].sg; in dcr_read_dma()
574 val = dma->sr; in dcr_read_dma()
576 default: in dcr_read_dma()
586 PPC4xxDmaState *dma = opaque; in dcr_write_dma() local
587 int addr = dcrn - dma->base; in dcr_write_dma()
594 dma->ch[chnl].cr = val; in dcr_write_dma()
596 int count = dma->ch[chnl].ct & 0xffff; in dcr_write_dma()
608 rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, in dcr_write_dma()
610 wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, in dcr_write_dma()
642 dma->ch[chnl].ct = val; in dcr_write_dma()
645 dma->ch[chnl].sa &= 0xffffffffULL; in dcr_write_dma()
646 dma->ch[chnl].sa |= (uint64_t)val << 32; in dcr_write_dma()
649 dma->ch[chnl].sa &= 0xffffffff00000000ULL; in dcr_write_dma()
650 dma->ch[chnl].sa |= val; in dcr_write_dma()
653 dma->ch[chnl].da &= 0xffffffffULL; in dcr_write_dma()
654 dma->ch[chnl].da |= (uint64_t)val << 32; in dcr_write_dma()
657 dma->ch[chnl].da &= 0xffffffff00000000ULL; in dcr_write_dma()
658 dma->ch[chnl].da |= val; in dcr_write_dma()
661 dma->ch[chnl].sg &= 0xffffffffULL; in dcr_write_dma()
662 dma->ch[chnl].sg |= (uint64_t)val << 32; in dcr_write_dma()
665 dma->ch[chnl].sg &= 0xffffffff00000000ULL; in dcr_write_dma()
666 dma->ch[chnl].sg |= val; in dcr_write_dma()
671 dma->sr &= ~val; in dcr_write_dma()
673 default: in dcr_write_dma()
681 PPC4xxDmaState *dma = opaque; in ppc4xx_dma_reset() local
682 int dma_base = dma->base; in ppc4xx_dma_reset()
684 memset(dma, 0, sizeof(*dma)); in ppc4xx_dma_reset()
685 dma->base = dma_base; in ppc4xx_dma_reset()
690 PPC4xxDmaState *dma; in ppc4xx_dma_init() local
693 dma = g_malloc0(sizeof(*dma)); in ppc4xx_dma_init()
694 dma->base = dcr_base; in ppc4xx_dma_init()
695 qemu_register_reset(&ppc4xx_dma_reset, dma); in ppc4xx_dma_init()
698 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
700 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
702 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
704 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
706 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
708 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
710 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
712 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
715 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
717 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
719 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
721 dma, &dcr_read_dma, &dcr_write_dma); in ppc4xx_dma_init()
791 switch (dcrn - s->dcrn_base) { in dcr_read_pcie()
793 ret = s->cfg_base >> 32; in dcr_read_pcie()
796 ret = s->cfg_base; in dcr_read_pcie()
799 ret = s->cfg_mask; in dcr_read_pcie()
802 ret = s->msg_base >> 32; in dcr_read_pcie()
805 ret = s->msg_base; in dcr_read_pcie()
808 ret = s->msg_mask; in dcr_read_pcie()
811 ret = s->omr1_base >> 32; in dcr_read_pcie()
814 ret = s->omr1_base; in dcr_read_pcie()
817 ret = s->omr1_mask >> 32; in dcr_read_pcie()
820 ret = s->omr1_mask; in dcr_read_pcie()
823 ret = s->omr2_base >> 32; in dcr_read_pcie()
826 ret = s->omr2_base; in dcr_read_pcie()
829 ret = s->omr2_mask >> 32; in dcr_read_pcie()
832 ret = s->omr3_mask; in dcr_read_pcie()
835 ret = s->omr3_base >> 32; in dcr_read_pcie()
838 ret = s->omr3_base; in dcr_read_pcie()
841 ret = s->omr3_mask >> 32; in dcr_read_pcie()
844 ret = s->omr3_mask; in dcr_read_pcie()
847 ret = s->reg_base >> 32; in dcr_read_pcie()
850 ret = s->reg_base; in dcr_read_pcie()
853 ret = s->reg_mask; in dcr_read_pcie()
856 ret = s->special; in dcr_read_pcie()
859 ret = s->cfg; in dcr_read_pcie()
871 switch (dcrn - s->dcrn_base) { in dcr_write_pcie()
873 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); in dcr_write_pcie()
876 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
879 s->cfg_mask = val; in dcr_write_pcie()
889 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); in dcr_write_pcie()
892 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); in dcr_write_pcie()
895 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
898 s->msg_mask = val; in dcr_write_pcie()
901 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); in dcr_write_pcie()
904 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
907 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); in dcr_write_pcie()
910 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
913 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); in dcr_write_pcie()
916 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
919 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); in dcr_write_pcie()
922 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
925 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); in dcr_write_pcie()
928 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
931 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); in dcr_write_pcie()
934 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
937 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); in dcr_write_pcie()
940 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
943 s->reg_mask = val; in dcr_write_pcie()
948 s->special = val; in dcr_write_pcie()
951 s->cfg = val; in dcr_write_pcie()
959 qemu_set_irq(s->irq[irq_num], level); in ppc460ex_set_irq()
963 ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
1001 if (!s->cpu) { in ppc460ex_pcie_realize()
1005 if (s->num < 0 || s->dcrn_base < 0) { in ppc460ex_pcie_realize()
1006 error_setg(errp, "busnum and dcrn-base properties must be set"); in ppc460ex_pcie_realize()
1009 snprintf(buf, sizeof(buf), "pcie%d-mem", s->num); in ppc460ex_pcie_realize()
1010 memory_region_init(&s->busmem, OBJECT(s), buf, UINT64_MAX); in ppc460ex_pcie_realize()
1011 snprintf(buf, sizeof(buf), "pcie%d-io", s->num); in ppc460ex_pcie_realize()
1012 memory_region_init(&s->iomem, OBJECT(s), buf, 64 * KiB); in ppc460ex_pcie_realize()
1014 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); in ppc460ex_pcie_realize()
1016 snprintf(buf, sizeof(buf), "pcie.%d", s->num); in ppc460ex_pcie_realize()
1017 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, in ppc460ex_pcie_realize()
1018 pci_swizzle_map_irq_fn, s, &s->busmem, in ppc460ex_pcie_realize()
1019 &s->iomem, 0, 4, TYPE_PCIE_BUS); in ppc460ex_pcie_realize()
1024 DEFINE_PROP_INT32("busnum", PPC460EXPCIEState, num, -1),
1025 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
1035 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); in ppc460ex_pcie_class_init()
1036 dc->realize = ppc460ex_pcie_realize; in ppc460ex_pcie_class_init()
1038 dc->hotpluggable = false; in ppc460ex_pcie_class_init()