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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
7 title: Renesas CPG DIV6 Clock
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
21 - renesas,r8a73a4-div6-clock # R-Mobile APE6
22 - renesas,r8a7740-div6-clock # R-Mobile A1
23 - renesas,sh73a0-div6-clock # SH-Mobile AG5
24 - const: renesas,cpg-div6-clock
67 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
H A Dtesla,fsd-clock.yaml115 - description: Shared0 PLL div6 clock (from CMU_CMU)
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dsh73a0.dtsi657 /* Variable factor clocks (DIV6) */
659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
[all …]
H A Dr8a73a4.dtsi493 /* Variable factor clocks (DIV6) */
495 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
503 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
510 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
517 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
524 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
531 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
538 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
546 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
554 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
[all …]
H A Dr8a7740.dtsi492 /* Variable factor clocks (DIV6) */
494 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
503 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
512 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
518 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
530 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
537 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
544 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
551 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
/openbmc/linux/drivers/clk/renesas/
H A Dclk-div6.c20 #include "clk-div6.h"
66 * DIV6 clocks require the divisor field to be non-zero when stopping in cpg_div6_clock_disable()
181 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", in cpg_div6_clock_get_parent()
218 * TODO: This does not yet support DIV6 clocks with multiple in cpg_div6_clock_notifier_call()
220 * Fortunately so far such DIV6 clocks are found only on in cpg_div6_clock_notifier_call()
235 * cpg_div6_register - Register a DIV6 clock
236 * @name: Name of the DIV6 clock
237 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
239 * @reg: Mapped register used to control the DIV6 clock
280 pr_err("%s: invalid number of parents for DIV6 clock %s\n", in cpg_div6_register()
[all …]
H A Drenesas-cpg-mssr.h36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
H A DMakefile51 obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o
H A DKconfig230 bool "DIV6 clock support" if COMPILE_TEST
H A Drenesas-cpg-mssr.c34 #include "clk-div6.h"
360 /* Multiply with the DIV6 register value */ in cpg_mssr_register_core_clk()
/openbmc/linux/arch/sh/lib/
H A Dudivsi3_i4i-Os.S39 bsr div6
42 bsr div6
59 div6: label
/openbmc/u-boot/arch/sh/lib/
H A Dudivsi3_i4i-Os.S39 bsr div6
42 bsr div6
59 div6: label
/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h58 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
59 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
H A Dclk-rcar-gen2.c129 case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */ in gen2_clk_get_rate()
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h40 u32 div6; /* 68 */ member
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Drenesas,rcar-can.yaml83 On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6
H A Drenesas,rcar-canfd.yaml72 Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
/openbmc/linux/drivers/sh/clk/
H A Dcpg.c170 * div6 clocks require the divisor field to be non-zero or the in sh_clk_div_disable()
261 * div6 support
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7724.c90 /* A fixed divide-by-3 block use by the div6 clocks */
274 /* DIV6 clocks */
H A Dclock-sh7722.c187 /* DIV6 clocks */
H A Dclock-sh7366.c200 /* DIV6 clocks */
H A Dclock-sh7343.c202 /* DIV6 clocks */
H A Dclock-sh7723.c212 /* DIV6 clocks */
/openbmc/linux/
H A Dopengrok2.0.log[all...]
H A Dopengrok0.0.log[all...]