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/openbmc/linux/include/soc/at91/
H A Dsama7-ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
24 #define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
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/openbmc/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLOCK_CTRL 0x00UL /* Main control */
14 #define CLOCK_PWRSTAT 0x30UL /* Power status */
15 #define CLOCK_PWRPRES 0x40UL /* Power presence */
18 #define CLOCK_PWRSTAT2 0x70UL /* Power status two */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
31 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
32 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
39 #define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
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/openbmc/linux/drivers/pci/pcie/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This enables PCI Express Port Bus support. Users can then enable
10 support for Native Hot-Plug, Advanced Error Reporting, Power
11 Management Events, and Downstream Port Containment.
33 This enables PCI Express Root Port Advanced Error Reporting
35 Port will be handled by PCI Express AER driver.
42 This enables PCI Express Root Port Advanced Error Reporting
46 to trigger various real hardware errors. Software-based
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/openbmc/linux/Documentation/sound/
H A Dalsa-configuration.rst2 Advanced Linux Sound Architecture - Driver Configuration guide
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
57 (0 = disable debug prints, 1 = normal debug messages,
63 Module snd-pcm-oss
64 ------------------
86 regarding opening the device. When this option is non-zero,
90 Module snd-rawmidi
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dpxa-usb.txt6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
11 If present, enables the appropriate USB port of the controller.
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci";
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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H A Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Li Jun <jun.li@nxp.com>
15 const: fsl,imx8mp-dwc3
19 - description: Address and length of the register set for HSIO Block Control
20 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
22 "#address-cells":
25 "#size-cells":
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H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/openbmc/linux/Documentation/driver-api/usb/
H A Dpower-management.rst1 .. _usb-power-management:
3 Power Management for USB
7 :Date: Last-updated: February 2014
11 ---------
12 * What is Power Management?
17 * Changing the default idle-delay time
19 * The driver interface for Power Management
25 * USB Port Power Control
26 * User Interface for Port Power Control
27 * Suggested Userspace Port Power Policy
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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/openbmc/linux/drivers/bus/
H A Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
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/openbmc/qemu/include/hw/usb/
H A Dehci-regs.h4 /* Capability Registers Base Address - section 2.2 */
5 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
6 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
7 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
8 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
24 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
25 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
31 #define USBSTS_PCD (1 << 2) // Port Change Detect
56 * Bits that are reserved or are read-only are masked out of values
64 #define PORTSC_PTC (15 << 16) // Port Test Control
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/openbmc/linux/drivers/pci/hotplug/
H A Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
36 pci_dbg(ctrl->pcie->port, format, ## arg)
38 pci_err(ctrl->pcie->port, format, ## arg)
40 pci_info(ctrl->pcie->port, format, ## arg)
42 pci_warn(ctrl->pcie->port, format, ## arg)
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
50 * @inband_presence_disabled: In-Band Presence Detect Disable supported by
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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-utmi.c1 // SPDX-License-Identifier: GPL-2.0
79 #define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000)
82 * struct mvebu_cp110_utmi - PHY driver data
97 * struct mvebu_cp110_utmi_port - PHY port data
100 * @id: PHY port ID
109 static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port *port) in mvebu_cp110_utmi_port_setup() argument
121 reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
125 writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
128 reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
131 writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG); in mvebu_cp110_utmi_port_setup()
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/openbmc/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt2 Advanced Configuration and Power Interface
5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
16 See also Documentation/power/runtime_pm.rst, pci=noacpi
26 If set to vendor, prefer vendor-specific driver
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/openbmc/linux/include/uapi/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
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/openbmc/u-boot/board/armltd/vexpress/
H A Dvexpress_tc2.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/u-boot.h>
27 * bit 12 = Use per-cpu mailboxes for power management in armv7_boot_nonsec_default()
28 * bit 13 = Power down the non-boot cluster in armv7_boot_nonsec_default()
30 * It is only when both of these are false that U-Boot's current in armv7_boot_nonsec_default()
43 const char *cci_compatible = "arm,cci-400-ctrl-if"; in ft_board_setup()
51 /* Booting in nonsec mode, disable CCI access */ in ft_board_setup()
58 /* delete cci-control-port in each cpu node */ in ft_board_setup()
61 fdt_delprop(fdt, tmp, "cci-control-port"); in ft_board_setup()
63 /* disable all ace cci slave ports */ in ft_board_setup()
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/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-octeon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2017 Cavium Networks
21 * USB Control Register
24 /* BIST fast-clear mode select. A BIST run with this bit set
39 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
41 /* Spread-spectrum clock modulation range:
42 * 0x0 = -4980 ppm downspread
43 * 0x1 = -4492 ppm downspread
44 * 0x2 = -4003 ppm downspread
45 * 0x3 - 0x7 = Reserved
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_pps.c1 // SPDX-License-Identifier: MIT
31 switch (pps->pps_pipe) { in pps_name()
43 MISSING_CASE(pps->pps_pipe); in pps_name()
47 switch (pps->pps_idx) { in pps_name()
53 MISSING_CASE(pps->pps_idx); in pps_name()
67 * See intel_pps_reset_all() why we need a power domain reference here. in intel_pps_lock()
70 mutex_lock(&dev_priv->display.pps.mutex); in intel_pps_lock()
80 mutex_unlock(&dev_priv->display.pps.mutex); in intel_pps_unlock()
91 enum pipe pipe = intel_dp->pps.pps_pipe; in vlv_power_sequencer_kick()
97 if (drm_WARN(&dev_priv->drm, in vlv_power_sequencer_kick()
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/openbmc/u-boot/drivers/ata/
H A Dmvsata_ide.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
19 /* SATA port registers */
42 * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
43 * - for ide_preinit to make sense, we need at least one of
45 * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
62 * Masks and values for SControl DETection and Interface Power Management,
85 * If/when standard negative codes are implemented in U-Boot, then these
91 #define MVSATA_STATUS_TIMEOUT -1
112 /* Disable windows, Set Size/Base to 0 */ in mvsata_ide_conf_mbus_windows()
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/openbmc/ipmitool/doc/
H A Dipmitool.13 ipmitool \- utility for controlling IPMI\-enabled devices
6 ipmitool [ <options> ] <command> [ <sub-commands and sub-options> ]
8 <options> := [ <general-options> | <conditional-opts> ]
13 <general-options> := [ -h | -V | -v | -I <interface> | -H <address> |
14 -d <N> | -p <port> | -c | -U <username> |
15 -L <privlvl> | -l <lun> | -m <local_address> |
16 -N <sec> | -R <count> | <password-option> |
17 <oem-option> | <bridge-options> ]
19 <conditional-opts> := [ <lan-options> | <lanplus-options> |
20 <command-options> ]
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/openbmc/qemu/include/standard-headers/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
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/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh4.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
15 #define SH4_PCICR 0x100 /* PCI Control Register */
35 #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
40 #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
41 #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
45 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
47 #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
81 #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-faraday.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
28 return !readl(&regs->usb.easstr); in ehci_is_fotg2xx()
41 ret = (void __iomem *)((ulong)ctrl->hcor - 0x10); in faraday_ehci_get_port_speed()
43 spd = OTGCSR_SPD(readl(&regs->otg.otgcsr)); in faraday_ehci_get_port_speed()
45 spd = BMCSR_SPD(readl(&regs->usb.bmcsr)); in faraday_ehci_get_port_speed()
58 printf("ehci-faraday: invalid device speed\n"); in faraday_ehci_get_port_speed()
65 uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) in faraday_ehci_get_portsc_register() argument
68 if (port) { in faraday_ehci_get_portsc_register()
70 debug("The request port(%d) is not configured\n", port); in faraday_ehci_get_portsc_register()
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/openbmc/linux/include/linux/usb/
H A Dehci_def.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001-2002 by David Brownell
9 #include <linux/usb/ehci-dbgp.h>
17 * some hosts treat caplength and hciversion as parts of a 32-bit
26 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
27 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
28 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
31 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
32 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
34 #define HCS_N_PORTS_MAX 15 /* N_PORTS valid 0x1-0xF */
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