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/openbmc/u-boot/arch/arm/include/asm/
H A Dmach-types.h7 #define __ASM_ARM_MACH_TYPE_H
10 #define MACH_TYPE_EBSA110 0
11 #define MACH_TYPE_RISCPC 1
12 #define MACH_TYPE_NEXUSPCI 3
13 #define MACH_TYPE_EBSA285 4
14 #define MACH_TYPE_NETWINDER 5
15 #define MACH_TYPE_CATS 6
16 #define MACH_TYPE_TBOX 7
17 #define MACH_TYPE_CO285 8
18 #define MACH_TYPE_CLPS7110 9
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/openbmc/u-boot/include/dt-bindings/soc/
H A Dimx_rsrc.h7 #define DT_BINDINGS_RSCRC_IMX_H
14 #define SC_R_A53 0
15 #define SC_R_A53_0 1
16 #define SC_R_A53_1 2
17 #define SC_R_A53_2 3
18 #define SC_R_A53_3 4
19 #define SC_R_A72 5
20 #define SC_R_A72_0 6
21 #define SC_R_A72_1 7
22 #define SC_R_A72_2 8
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/openbmc/u-boot/include/dt-bindings/clock/
H A Dimx8qxp-clock.h7 #define __DT_BINDINGS_CLOCK_IMX8QXP_H
9 #define IMX8QXP_CLK_DUMMY 0
11 #define IMX8QXP_UART0_IPG_CLK 1
12 #define IMX8QXP_UART0_DIV 2
13 #define IMX8QXP_UART0_CLK 3
15 #define IMX8QXP_IPG_DMA_CLK_ROOT 4
18 #define IMX8QXP_GPU0_CORE_DIV 5
19 #define IMX8QXP_GPU0_CORE_CLK 6
20 #define IMX8QXP_GPU0_SHADER_DIV 7
21 #define IMX8QXP_GPU0_SHADER_CLK 8
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H A Drk3399-cru.h7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
10 #define PLL_APLLL 1
11 #define PLL_APLLB 2
12 #define PLL_DPLL 3
13 #define PLL_CPLL 4
14 #define PLL_GPLL 5
15 #define PLL_NPLL 6
16 #define PLL_VPLL 7
17 #define ARMCLKL 8
18 #define ARMCLKB 9
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H A Dimx7d-clock.h11 #define __DT_BINDINGS_CLOCK_IMX7D_H
13 #define IMX7D_OSC_24M_CLK 0
14 #define IMX7D_PLL_ARM_MAIN 1
15 #define IMX7D_PLL_ARM_MAIN_CLK 2
16 #define IMX7D_PLL_ARM_MAIN_SRC 3
17 #define IMX7D_PLL_ARM_MAIN_BYPASS 4
18 #define IMX7D_PLL_SYS_MAIN 5
19 #define IMX7D_PLL_SYS_MAIN_CLK 6
20 #define IMX7D_PLL_SYS_MAIN_SRC 7
21 #define IMX7D_PLL_SYS_MAIN_BYPASS 8
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H A Drk3328-cru.h7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
10 #define PLL_APLL 1
11 #define PLL_DPLL 2
12 #define PLL_CPLL 3
13 #define PLL_GPLL 4
14 #define PLL_NPLL 5
15 #define ARMCLK 6
18 #define SCLK_RTC32K 30
19 #define SCLK_SDMMC_EXT 31
20 #define SCLK_SPI 32
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H A Dmt7623-clk.h7 #define _DT_BINDINGS_CLK_MT2701_H
10 #define CLK_TOP_FCLKS_OFF 0
12 #define CLK_TOP_DPI 0
13 #define CLK_TOP_DMPLL 1
14 #define CLK_TOP_VENCPLL 2
15 #define CLK_TOP_HDMI_0_PIX340M 3
16 #define CLK_TOP_HDMI_0_DEEP340M 4
17 #define CLK_TOP_HDMI_0_PLL340M 5
18 #define CLK_TOP_HADDS2_FB 6
19 #define CLK_TOP_WBG_DIG_416M 7
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H A Drv1108-cru.h8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
11 #define PLL_APLL 0
12 #define PLL_DPLL 1
13 #define PLL_GPLL 2
14 #define ARMCLK 3
17 #define SCLK_SPI0 65
18 #define SCLK_NANDC 67
19 #define SCLK_SDMMC 68
20 #define SCLK_SDIO 69
21 #define SCLK_EMMC 71
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/openbmc/qemu/linux-headers/asm-powerpc/
H A Dunistd_32.h2 #define _ASM_UNISTD_32_H
4 #define __NR_restart_syscall 0
5 #define __NR_exit 1
6 #define __NR_fork 2
7 #define __NR_read 3
8 #define __NR_write 4
9 #define __NR_open 5
10 #define __NR_close 6
11 #define __NR_waitpid 7
12 #define __NR_creat 8
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H A Dunistd_64.h2 #define _ASM_UNISTD_64_H
4 #define __NR_restart_syscall 0
5 #define __NR_exit 1
6 #define __NR_fork 2
7 #define __NR_read 3
8 #define __NR_write 4
9 #define __NR_open 5
10 #define __NR_close 6
11 #define __NR_waitpid 7
12 #define __NR_creat 8
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/openbmc/qemu/linux-headers/asm-s390/
H A Dunistd_32.h3 #define _ASM_S390_UNISTD_32_H
5 #define __NR_exit 1
6 #define __NR_fork 2
7 #define __NR_read 3
8 #define __NR_write 4
9 #define __NR_open 5
10 #define __NR_close 6
11 #define __NR_restart_syscall 7
12 #define __NR_creat 8
13 #define __NR_link 9
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H A Dunistd_64.h3 #define _ASM_S390_UNISTD_64_H
5 #define __NR_exit 1
6 #define __NR_fork 2
7 #define __NR_read 3
8 #define __NR_write 4
9 #define __NR_open 5
10 #define __NR_close 6
11 #define __NR_restart_syscall 7
12 #define __NR_creat 8
13 #define __NR_link 9
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/openbmc/qemu/linux-headers/asm-x86/
H A Dunistd_32.h2 #define _ASM_UNISTD_32_H
4 #define __NR_restart_syscall 0
5 #define __NR_exit 1
6 #define __NR_fork 2
7 #define __NR_read 3
8 #define __NR_write 4
9 #define __NR_open 5
10 #define __NR_close 6
11 #define __NR_waitpid 7
12 #define __NR_creat 8
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H A Dunistd_64.h2 #define _ASM_UNISTD_64_H
4 #define __NR_read 0
5 #define __NR_write 1
6 #define __NR_open 2
7 #define __NR_close 3
8 #define __NR_stat 4
9 #define __NR_fstat 5
10 #define __NR_lstat 6
11 #define __NR_poll 7
12 #define __NR_lseek 8
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/openbmc/u-boot/drivers/video/meson/
H A Dmeson_registers.h7 #define __MESON_REGISTERS_H
10 #define _REG(reg) ((reg) << 2)
12 #define writel_bits(mask, val, addr) \
16 #define VPP2_DUMMY_DATA 0x1900
17 #define VPP2_LINE_IN_LENGTH 0x1901
18 #define VPP2_PIC_IN_HEIGHT 0x1902
19 #define VPP2_SCALE_COEF_IDX 0x1903
20 #define VPP2_SCALE_COEF 0x1904
21 #define VPP2_VSC_REGION12_STARTP 0x1905
22 #define VPP2_VSC_REGION34_STARTP 0x1906
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/openbmc/qemu/linux-headers/asm-loongarch/
H A Dunistd_64.h2 #define _ASM_UNISTD_64_H
4 #define __NR_io_setup 0
5 #define __NR_io_destroy 1
6 #define __NR_io_submit 2
7 #define __NR_io_cancel 3
8 #define __NR_io_getevents 4
9 #define __NR_setxattr 5
10 #define __NR_lsetxattr 6
11 #define __NR_fsetxattr 7
12 #define __NR_getxattr 8
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/openbmc/u-boot/include/
H A Dpci_ids.h12 #define PCI_CLASS_NOT_DEFINED 0x0000
13 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
15 #define PCI_BASE_CLASS_STORAGE 0x01
16 #define PCI_CLASS_STORAGE_SCSI 0x0100
17 #define PCI_CLASS_STORAGE_IDE 0x0101
18 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
19 #define PCI_CLASS_STORAGE_IPI 0x0103
20 #define PCI_CLASS_STORAGE_RAID 0x0104
21 #define PCI_CLASS_STORAGE_SATA 0x0106
22 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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H A Dradeon.h2 #define _RADEON_H
5 #define RADEON_REGSIZE 0x4000
8 #define MM_INDEX 0x0000
9 #define MM_DATA 0x0004
10 #define BUS_CNTL 0x0030
11 #define HI_STAT 0x004C
12 #define BUS_CNTL1 0x0034
13 #define I2C_CNTL_1 0x0094
14 #define CONFIG_CNTL 0x00E0
15 #define CONFIG_MEMSIZE 0x00F8
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/openbmc/qemu/bsd-user/netbsd/
H A Dsyscall_nr.h9 #define TARGET_NETBSD_NR_syscall 0
10 #define TARGET_NETBSD_NR_exit 1
11 #define TARGET_NETBSD_NR_fork 2
12 #define TARGET_NETBSD_NR_read 3
13 #define TARGET_NETBSD_NR_write 4
14 #define TARGET_NETBSD_NR_open 5
15 #define TARGET_NETBSD_NR_close 6
16 #define TARGET_NETBSD_NR_wait4 7
17 #define TARGET_NETBSD_NR_compat_43_ocreat 8
18 #define TARGET_NETBSD_NR_link 9
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/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32h7-pinfunc.h2 #define _DT_BINDINGS_STM32H7_PINFUNC_H
4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
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H A Dstm32f746-pinfunc.h2 #define _DT_BINDINGS_STM32F746_PINFUNC_H
4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
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/openbmc/qemu/linux-headers/asm-riscv/
H A Dunistd_32.h2 #define _ASM_UNISTD_32_H
4 #define __NR_io_setup 0
5 #define __NR_io_destroy 1
6 #define __NR_io_submit 2
7 #define __NR_io_cancel 3
8 #define __NR_setxattr 5
9 #define __NR_lsetxattr 6
10 #define __NR_fsetxattr 7
11 #define __NR_getxattr 8
12 #define __NR_lgetxattr 9
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H A Dunistd_64.h2 #define _ASM_UNISTD_64_H
4 #define __NR_io_setup 0
5 #define __NR_io_destroy 1
6 #define __NR_io_submit 2
7 #define __NR_io_cancel 3
8 #define __NR_io_getevents 4
9 #define __NR_setxattr 5
10 #define __NR_lsetxattr 6
11 #define __NR_fsetxattr 7
12 #define __NR_getxattr 8
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/openbmc/qemu/linux-headers/asm-arm64/
H A Dunistd_64.h2 #define _ASM_UNISTD_64_H
4 #define __NR_io_setup 0
5 #define __NR_io_destroy 1
6 #define __NR_io_submit 2
7 #define __NR_io_cancel 3
8 #define __NR_io_getevents 4
9 #define __NR_setxattr 5
10 #define __NR_lsetxattr 6
11 #define __NR_fsetxattr 7
12 #define __NR_getxattr 8
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/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7722.h9 #define _ASM_CPU_SH7722_H_
11 #define CACHE_OC_NUM_WAYS 4
12 #define CCR_CACHE_INIT 0x0000090d
15 #define TRA 0xFF000020
16 #define EXPEVT 0xFF000024
17 #define INTEVT 0xFF000028
20 #define PTEH 0xFF000000
21 #define PTEL 0xFF000004
22 #define TTB 0xFF000008
23 #define TEA 0xFF00000C
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