15072188aSJason Jin #ifndef _RADEON_H 25072188aSJason Jin #define _RADEON_H 35072188aSJason Jin 45072188aSJason Jin 55072188aSJason Jin #define RADEON_REGSIZE 0x4000 65072188aSJason Jin 75072188aSJason Jin 85072188aSJason Jin #define MM_INDEX 0x0000 95072188aSJason Jin #define MM_DATA 0x0004 105072188aSJason Jin #define BUS_CNTL 0x0030 115072188aSJason Jin #define HI_STAT 0x004C 125072188aSJason Jin #define BUS_CNTL1 0x0034 135072188aSJason Jin #define I2C_CNTL_1 0x0094 145072188aSJason Jin #define CONFIG_CNTL 0x00E0 155072188aSJason Jin #define CONFIG_MEMSIZE 0x00F8 165072188aSJason Jin #define CONFIG_APER_0_BASE 0x0100 175072188aSJason Jin #define CONFIG_APER_1_BASE 0x0104 185072188aSJason Jin #define CONFIG_APER_SIZE 0x0108 195072188aSJason Jin #define CONFIG_REG_1_BASE 0x010C 205072188aSJason Jin #define CONFIG_REG_APER_SIZE 0x0110 215072188aSJason Jin #define PAD_AGPINPUT_DELAY 0x0164 225072188aSJason Jin #define PAD_CTLR_STRENGTH 0x0168 235072188aSJason Jin #define PAD_CTLR_UPDATE 0x016C 245072188aSJason Jin #define PAD_CTLR_MISC 0x0aa0 255072188aSJason Jin #define AGP_CNTL 0x0174 265072188aSJason Jin #define BM_STATUS 0x0160 275072188aSJason Jin #define CAP0_TRIG_CNTL 0x0950 285072188aSJason Jin #define CAP1_TRIG_CNTL 0x09c0 295072188aSJason Jin #define VIPH_CONTROL 0x0C40 305072188aSJason Jin #define VENDOR_ID 0x0F00 315072188aSJason Jin #define DEVICE_ID 0x0F02 325072188aSJason Jin #define COMMAND 0x0F04 335072188aSJason Jin #define STATUS 0x0F06 345072188aSJason Jin #define REVISION_ID 0x0F08 355072188aSJason Jin #define REGPROG_INF 0x0F09 365072188aSJason Jin #define SUB_CLASS 0x0F0A 375072188aSJason Jin #define BASE_CODE 0x0F0B 385072188aSJason Jin #define CACHE_LINE 0x0F0C 395072188aSJason Jin #define LATENCY 0x0F0D 405072188aSJason Jin #define HEADER 0x0F0E 415072188aSJason Jin #define BIST 0x0F0F 425072188aSJason Jin #define REG_MEM_BASE 0x0F10 435072188aSJason Jin #define REG_IO_BASE 0x0F14 445072188aSJason Jin #define REG_REG_BASE 0x0F18 455072188aSJason Jin #define ADAPTER_ID 0x0F2C 465072188aSJason Jin #define BIOS_ROM 0x0F30 475072188aSJason Jin #define CAPABILITIES_PTR 0x0F34 485072188aSJason Jin #define INTERRUPT_LINE 0x0F3C 495072188aSJason Jin #define INTERRUPT_PIN 0x0F3D 505072188aSJason Jin #define MIN_GRANT 0x0F3E 515072188aSJason Jin #define MAX_LATENCY 0x0F3F 525072188aSJason Jin #define ADAPTER_ID_W 0x0F4C 535072188aSJason Jin #define PMI_CAP_ID 0x0F50 545072188aSJason Jin #define PMI_NXT_CAP_PTR 0x0F51 555072188aSJason Jin #define PMI_PMC_REG 0x0F52 565072188aSJason Jin #define PM_STATUS 0x0F54 575072188aSJason Jin #define PMI_DATA 0x0F57 585072188aSJason Jin #define AGP_CAP_ID 0x0F58 595072188aSJason Jin #define AGP_STATUS 0x0F5C 605072188aSJason Jin #define AGP_COMMAND 0x0F60 615072188aSJason Jin #define AIC_CTRL 0x01D0 625072188aSJason Jin #define AIC_STAT 0x01D4 635072188aSJason Jin #define AIC_PT_BASE 0x01D8 645072188aSJason Jin #define AIC_LO_ADDR 0x01DC 655072188aSJason Jin #define AIC_HI_ADDR 0x01E0 665072188aSJason Jin #define AIC_TLB_ADDR 0x01E4 675072188aSJason Jin #define AIC_TLB_DATA 0x01E8 685072188aSJason Jin #define DAC_CNTL 0x0058 695072188aSJason Jin #define DAC_CNTL2 0x007c 705072188aSJason Jin #define CRTC_GEN_CNTL 0x0050 715072188aSJason Jin #define MEM_CNTL 0x0140 725072188aSJason Jin #define MC_CNTL 0x0140 735072188aSJason Jin #define EXT_MEM_CNTL 0x0144 745072188aSJason Jin #define MC_TIMING_CNTL 0x0144 755072188aSJason Jin #define MC_AGP_LOCATION 0x014C 765072188aSJason Jin #define MEM_IO_CNTL_A0 0x0178 775072188aSJason Jin #define MEM_REFRESH_CNTL 0x0178 785072188aSJason Jin #define MEM_INIT_LATENCY_TIMER 0x0154 795072188aSJason Jin #define MC_INIT_GFX_LAT_TIMER 0x0154 805072188aSJason Jin #define MEM_SDRAM_MODE_REG 0x0158 815072188aSJason Jin #define AGP_BASE 0x0170 825072188aSJason Jin #define MEM_IO_CNTL_A1 0x017C 835072188aSJason Jin #define MC_READ_CNTL_AB 0x017C 845072188aSJason Jin #define MEM_IO_CNTL_B0 0x0180 855072188aSJason Jin #define MC_INIT_MISC_LAT_TIMER 0x0180 865072188aSJason Jin #define MEM_IO_CNTL_B1 0x0184 875072188aSJason Jin #define MC_IOPAD_CNTL 0x0184 885072188aSJason Jin #define MC_DEBUG 0x0188 895072188aSJason Jin #define MC_STATUS 0x0150 905072188aSJason Jin #define MEM_IO_OE_CNTL 0x018C 915072188aSJason Jin #define MC_CHIP_IO_OE_CNTL_AB 0x018C 925072188aSJason Jin #define MC_FB_LOCATION 0x0148 939c7e4b06SWolfgang Denk /* #define MC_FB_LOCATION 0x0188 */ 945072188aSJason Jin #define HOST_PATH_CNTL 0x0130 955072188aSJason Jin #define MEM_VGA_WP_SEL 0x0038 965072188aSJason Jin #define MEM_VGA_RP_SEL 0x003C 975072188aSJason Jin #define HDP_DEBUG 0x0138 985072188aSJason Jin #define SW_SEMAPHORE 0x013C 995072188aSJason Jin #define CRTC2_GEN_CNTL 0x03f8 1005072188aSJason Jin #define CRTC2_DISPLAY_BASE_ADDR 0x033c 1015072188aSJason Jin #define SURFACE_CNTL 0x0B00 1025072188aSJason Jin #define SURFACE0_LOWER_BOUND 0x0B04 1035072188aSJason Jin #define SURFACE1_LOWER_BOUND 0x0B14 1045072188aSJason Jin #define SURFACE2_LOWER_BOUND 0x0B24 1055072188aSJason Jin #define SURFACE3_LOWER_BOUND 0x0B34 1065072188aSJason Jin #define SURFACE4_LOWER_BOUND 0x0B44 1075072188aSJason Jin #define SURFACE5_LOWER_BOUND 0x0B54 1085072188aSJason Jin #define SURFACE6_LOWER_BOUND 0x0B64 1095072188aSJason Jin #define SURFACE7_LOWER_BOUND 0x0B74 1105072188aSJason Jin #define SURFACE0_UPPER_BOUND 0x0B08 1115072188aSJason Jin #define SURFACE1_UPPER_BOUND 0x0B18 1125072188aSJason Jin #define SURFACE2_UPPER_BOUND 0x0B28 1135072188aSJason Jin #define SURFACE3_UPPER_BOUND 0x0B38 1145072188aSJason Jin #define SURFACE4_UPPER_BOUND 0x0B48 1155072188aSJason Jin #define SURFACE5_UPPER_BOUND 0x0B58 1165072188aSJason Jin #define SURFACE6_UPPER_BOUND 0x0B68 1175072188aSJason Jin #define SURFACE7_UPPER_BOUND 0x0B78 1185072188aSJason Jin #define SURFACE0_INFO 0x0B0C 1195072188aSJason Jin #define SURFACE1_INFO 0x0B1C 1205072188aSJason Jin #define SURFACE2_INFO 0x0B2C 1215072188aSJason Jin #define SURFACE3_INFO 0x0B3C 1225072188aSJason Jin #define SURFACE4_INFO 0x0B4C 1235072188aSJason Jin #define SURFACE5_INFO 0x0B5C 1245072188aSJason Jin #define SURFACE6_INFO 0x0B6C 1255072188aSJason Jin #define SURFACE7_INFO 0x0B7C 1265072188aSJason Jin #define SURFACE_ACCESS_FLAGS 0x0BF8 1275072188aSJason Jin #define SURFACE_ACCESS_CLR 0x0BFC 1285072188aSJason Jin #define GEN_INT_CNTL 0x0040 1295072188aSJason Jin #define GEN_INT_STATUS 0x0044 1305072188aSJason Jin #define CRTC_EXT_CNTL 0x0054 1315072188aSJason Jin #define RB3D_CNTL 0x1C3C 1325072188aSJason Jin #define WAIT_UNTIL 0x1720 1335072188aSJason Jin #define ISYNC_CNTL 0x1724 1345072188aSJason Jin #define RBBM_GUICNTL 0x172C 1355072188aSJason Jin #define RBBM_STATUS 0x0E40 1365072188aSJason Jin #define RBBM_STATUS_alt_1 0x1740 1375072188aSJason Jin #define RBBM_CNTL 0x00EC 1385072188aSJason Jin #define RBBM_CNTL_alt_1 0x0E44 1395072188aSJason Jin #define RBBM_SOFT_RESET 0x00F0 1405072188aSJason Jin #define RBBM_SOFT_RESET_alt_1 0x0E48 1415072188aSJason Jin #define NQWAIT_UNTIL 0x0E50 1425072188aSJason Jin #define RBBM_DEBUG 0x0E6C 1435072188aSJason Jin #define RBBM_CMDFIFO_ADDR 0x0E70 1445072188aSJason Jin #define RBBM_CMDFIFO_DATAL 0x0E74 1455072188aSJason Jin #define RBBM_CMDFIFO_DATAH 0x0E78 1465072188aSJason Jin #define RBBM_CMDFIFO_STAT 0x0E7C 1475072188aSJason Jin #define CRTC_STATUS 0x005C 1485072188aSJason Jin #define GPIO_VGA_DDC 0x0060 1495072188aSJason Jin #define GPIO_DVI_DDC 0x0064 1505072188aSJason Jin #define GPIO_MONID 0x0068 1515072188aSJason Jin #define GPIO_CRT2_DDC 0x006c 1525072188aSJason Jin #define PALETTE_INDEX 0x00B0 1535072188aSJason Jin #define PALETTE_DATA 0x00B4 1545072188aSJason Jin #define PALETTE_30_DATA 0x00B8 1555072188aSJason Jin #define CRTC_H_TOTAL_DISP 0x0200 1565072188aSJason Jin #define CRTC_H_SYNC_STRT_WID 0x0204 1571b8607e1SAnatolij Gustschin #define CRTC_H_SYNC_POL (1 << 23) 1585072188aSJason Jin #define CRTC_V_TOTAL_DISP 0x0208 1595072188aSJason Jin #define CRTC_V_SYNC_STRT_WID 0x020C 1601b8607e1SAnatolij Gustschin #define CRTC_V_SYNC_POL (1 << 23) 1615072188aSJason Jin #define CRTC_VLINE_CRNT_VLINE 0x0210 1625072188aSJason Jin #define CRTC_CRNT_FRAME 0x0214 1635072188aSJason Jin #define CRTC_GUI_TRIG_VLINE 0x0218 1645072188aSJason Jin #define CRTC_DEBUG 0x021C 1655072188aSJason Jin #define CRTC_OFFSET_RIGHT 0x0220 1665072188aSJason Jin #define CRTC_OFFSET 0x0224 1675072188aSJason Jin #define CRTC_OFFSET_CNTL 0x0228 1685072188aSJason Jin #define CRTC_PITCH 0x022C 1695072188aSJason Jin #define OVR_CLR 0x0230 1705072188aSJason Jin #define OVR_WID_LEFT_RIGHT 0x0234 1715072188aSJason Jin #define OVR_WID_TOP_BOTTOM 0x0238 1725072188aSJason Jin #define DISPLAY_BASE_ADDR 0x023C 1735072188aSJason Jin #define SNAPSHOT_VH_COUNTS 0x0240 1745072188aSJason Jin #define SNAPSHOT_F_COUNT 0x0244 1755072188aSJason Jin #define N_VIF_COUNT 0x0248 1765072188aSJason Jin #define SNAPSHOT_VIF_COUNT 0x024C 1775072188aSJason Jin #define FP_CRTC_H_TOTAL_DISP 0x0250 1785072188aSJason Jin #define FP_CRTC_V_TOTAL_DISP 0x0254 1795072188aSJason Jin #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 1805072188aSJason Jin #define CRT_CRTC_V_SYNC_STRT_WID 0x025C 1815072188aSJason Jin #define CUR_OFFSET 0x0260 1825072188aSJason Jin #define CUR_HORZ_VERT_POSN 0x0264 1835072188aSJason Jin #define CUR_HORZ_VERT_OFF 0x0268 1845072188aSJason Jin #define CUR_CLR0 0x026C 1855072188aSJason Jin #define CUR_CLR1 0x0270 1865072188aSJason Jin #define FP_HORZ_VERT_ACTIVE 0x0278 1875072188aSJason Jin #define CRTC_MORE_CNTL 0x027C 1885072188aSJason Jin #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 1895072188aSJason Jin #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 1905072188aSJason Jin #define DAC_EXT_CNTL 0x0280 1915072188aSJason Jin #define FP_GEN_CNTL 0x0284 1925072188aSJason Jin #define FP_HORZ_STRETCH 0x028C 1935072188aSJason Jin #define FP_VERT_STRETCH 0x0290 1945072188aSJason Jin #define FP_H_SYNC_STRT_WID 0x02C4 1955072188aSJason Jin #define FP_V_SYNC_STRT_WID 0x02C8 1965072188aSJason Jin #define AUX_WINDOW_HORZ_CNTL 0x02D8 1975072188aSJason Jin #define AUX_WINDOW_VERT_CNTL 0x02DC 1989c7e4b06SWolfgang Denk /* #define DDA_CONFIG 0x02e0 */ 1999c7e4b06SWolfgang Denk /* #define DDA_ON_OFF 0x02e4 */ 2005072188aSJason Jin #define DVI_I2C_CNTL_1 0x02e4 2015072188aSJason Jin #define GRPH_BUFFER_CNTL 0x02F0 2025072188aSJason Jin #define GRPH2_BUFFER_CNTL 0x03F0 2035072188aSJason Jin #define VGA_BUFFER_CNTL 0x02F4 2045072188aSJason Jin #define OV0_Y_X_START 0x0400 2055072188aSJason Jin #define OV0_Y_X_END 0x0404 2065072188aSJason Jin #define OV0_PIPELINE_CNTL 0x0408 2075072188aSJason Jin #define OV0_REG_LOAD_CNTL 0x0410 2085072188aSJason Jin #define OV0_SCALE_CNTL 0x0420 2095072188aSJason Jin #define OV0_V_INC 0x0424 2105072188aSJason Jin #define OV0_P1_V_ACCUM_INIT 0x0428 2115072188aSJason Jin #define OV0_P23_V_ACCUM_INIT 0x042C 2125072188aSJason Jin #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 2135072188aSJason Jin #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 2145072188aSJason Jin #define OV0_BASE_ADDR 0x043C 2155072188aSJason Jin #define OV0_VID_BUF0_BASE_ADRS 0x0440 2165072188aSJason Jin #define OV0_VID_BUF1_BASE_ADRS 0x0444 2175072188aSJason Jin #define OV0_VID_BUF2_BASE_ADRS 0x0448 2185072188aSJason Jin #define OV0_VID_BUF3_BASE_ADRS 0x044C 2195072188aSJason Jin #define OV0_VID_BUF4_BASE_ADRS 0x0450 2205072188aSJason Jin #define OV0_VID_BUF5_BASE_ADRS 0x0454 2215072188aSJason Jin #define OV0_VID_BUF_PITCH0_VALUE 0x0460 2225072188aSJason Jin #define OV0_VID_BUF_PITCH1_VALUE 0x0464 2235072188aSJason Jin #define OV0_AUTO_FLIP_CNTRL 0x0470 2245072188aSJason Jin #define OV0_DEINTERLACE_PATTERN 0x0474 2255072188aSJason Jin #define OV0_SUBMIT_HISTORY 0x0478 2265072188aSJason Jin #define OV0_H_INC 0x0480 2275072188aSJason Jin #define OV0_STEP_BY 0x0484 2285072188aSJason Jin #define OV0_P1_H_ACCUM_INIT 0x0488 2295072188aSJason Jin #define OV0_P23_H_ACCUM_INIT 0x048C 2305072188aSJason Jin #define OV0_P1_X_START_END 0x0494 2315072188aSJason Jin #define OV0_P2_X_START_END 0x0498 2325072188aSJason Jin #define OV0_P3_X_START_END 0x049C 2335072188aSJason Jin #define OV0_FILTER_CNTL 0x04A0 2345072188aSJason Jin #define OV0_FOUR_TAP_COEF_0 0x04B0 2355072188aSJason Jin #define OV0_FOUR_TAP_COEF_1 0x04B4 2365072188aSJason Jin #define OV0_FOUR_TAP_COEF_2 0x04B8 2375072188aSJason Jin #define OV0_FOUR_TAP_COEF_3 0x04BC 2385072188aSJason Jin #define OV0_FOUR_TAP_COEF_4 0x04C0 2395072188aSJason Jin #define OV0_FLAG_CNTRL 0x04DC 2405072188aSJason Jin #define OV0_SLICE_CNTL 0x04E0 2415072188aSJason Jin #define OV0_VID_KEY_CLR_LOW 0x04E4 2425072188aSJason Jin #define OV0_VID_KEY_CLR_HIGH 0x04E8 2435072188aSJason Jin #define OV0_GRPH_KEY_CLR_LOW 0x04EC 2445072188aSJason Jin #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 2455072188aSJason Jin #define OV0_KEY_CNTL 0x04F4 2465072188aSJason Jin #define OV0_TEST 0x04F8 2475072188aSJason Jin #define SUBPIC_CNTL 0x0540 2485072188aSJason Jin #define SUBPIC_DEFCOLCON 0x0544 2495072188aSJason Jin #define SUBPIC_Y_X_START 0x054C 2505072188aSJason Jin #define SUBPIC_Y_X_END 0x0550 2515072188aSJason Jin #define SUBPIC_V_INC 0x0554 2525072188aSJason Jin #define SUBPIC_H_INC 0x0558 2535072188aSJason Jin #define SUBPIC_BUF0_OFFSET 0x055C 2545072188aSJason Jin #define SUBPIC_BUF1_OFFSET 0x0560 2555072188aSJason Jin #define SUBPIC_LC0_OFFSET 0x0564 2565072188aSJason Jin #define SUBPIC_LC1_OFFSET 0x0568 2575072188aSJason Jin #define SUBPIC_PITCH 0x056C 2585072188aSJason Jin #define SUBPIC_BTN_HLI_COLCON 0x0570 2595072188aSJason Jin #define SUBPIC_BTN_HLI_Y_X_START 0x0574 2605072188aSJason Jin #define SUBPIC_BTN_HLI_Y_X_END 0x0578 2615072188aSJason Jin #define SUBPIC_PALETTE_INDEX 0x057C 2625072188aSJason Jin #define SUBPIC_PALETTE_DATA 0x0580 2635072188aSJason Jin #define SUBPIC_H_ACCUM_INIT 0x0584 2645072188aSJason Jin #define SUBPIC_V_ACCUM_INIT 0x0588 2655072188aSJason Jin #define DISP_MISC_CNTL 0x0D00 2665072188aSJason Jin #define DAC_MACRO_CNTL 0x0D04 2675072188aSJason Jin #define DISP_PWR_MAN 0x0D08 2685072188aSJason Jin #define DISP_TEST_DEBUG_CNTL 0x0D10 2695072188aSJason Jin #define DISP_HW_DEBUG 0x0D14 2705072188aSJason Jin #define DAC_CRC_SIG1 0x0D18 2715072188aSJason Jin #define DAC_CRC_SIG2 0x0D1C 2725072188aSJason Jin #define OV0_LIN_TRANS_A 0x0D20 2735072188aSJason Jin #define OV0_LIN_TRANS_B 0x0D24 2745072188aSJason Jin #define OV0_LIN_TRANS_C 0x0D28 2755072188aSJason Jin #define OV0_LIN_TRANS_D 0x0D2C 2765072188aSJason Jin #define OV0_LIN_TRANS_E 0x0D30 2775072188aSJason Jin #define OV0_LIN_TRANS_F 0x0D34 2785072188aSJason Jin #define OV0_GAMMA_0_F 0x0D40 2795072188aSJason Jin #define OV0_GAMMA_10_1F 0x0D44 2805072188aSJason Jin #define OV0_GAMMA_20_3F 0x0D48 2815072188aSJason Jin #define OV0_GAMMA_40_7F 0x0D4C 2825072188aSJason Jin #define OV0_GAMMA_380_3BF 0x0D50 2835072188aSJason Jin #define OV0_GAMMA_3C0_3FF 0x0D54 2845072188aSJason Jin #define DISP_MERGE_CNTL 0x0D60 2855072188aSJason Jin #define DISP_OUTPUT_CNTL 0x0D64 2865072188aSJason Jin #define DISP_LIN_TRANS_GRPH_A 0x0D80 2875072188aSJason Jin #define DISP_LIN_TRANS_GRPH_B 0x0D84 2885072188aSJason Jin #define DISP_LIN_TRANS_GRPH_C 0x0D88 2895072188aSJason Jin #define DISP_LIN_TRANS_GRPH_D 0x0D8C 2905072188aSJason Jin #define DISP_LIN_TRANS_GRPH_E 0x0D90 2915072188aSJason Jin #define DISP_LIN_TRANS_GRPH_F 0x0D94 2925072188aSJason Jin #define DISP_LIN_TRANS_VID_A 0x0D98 2935072188aSJason Jin #define DISP_LIN_TRANS_VID_B 0x0D9C 2945072188aSJason Jin #define DISP_LIN_TRANS_VID_C 0x0DA0 2955072188aSJason Jin #define DISP_LIN_TRANS_VID_D 0x0DA4 2965072188aSJason Jin #define DISP_LIN_TRANS_VID_E 0x0DA8 2975072188aSJason Jin #define DISP_LIN_TRANS_VID_F 0x0DAC 2985072188aSJason Jin #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 2995072188aSJason Jin #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 3005072188aSJason Jin #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 3015072188aSJason Jin #define RMX_HORZ_PHASE 0x0DBC 3025072188aSJason Jin #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 3035072188aSJason Jin #define DAC_BROAD_PULSE 0x0DC4 3045072188aSJason Jin #define DAC_SKEW_CLKS 0x0DC8 3055072188aSJason Jin #define DAC_INCR 0x0DCC 3065072188aSJason Jin #define DAC_NEG_SYNC_LEVEL 0x0DD0 3075072188aSJason Jin #define DAC_POS_SYNC_LEVEL 0x0DD4 3085072188aSJason Jin #define DAC_BLANK_LEVEL 0x0DD8 3095072188aSJason Jin #define CLOCK_CNTL_INDEX 0x0008 3105072188aSJason Jin #define CLOCK_CNTL_DATA 0x000C 3115072188aSJason Jin #define CP_RB_CNTL 0x0704 3125072188aSJason Jin #define CP_RB_BASE 0x0700 3135072188aSJason Jin #define CP_RB_RPTR_ADDR 0x070C 3145072188aSJason Jin #define CP_RB_RPTR 0x0710 3155072188aSJason Jin #define CP_RB_WPTR 0x0714 3165072188aSJason Jin #define CP_RB_WPTR_DELAY 0x0718 3175072188aSJason Jin #define CP_IB_BASE 0x0738 3185072188aSJason Jin #define CP_IB_BUFSZ 0x073C 3195072188aSJason Jin #define SCRATCH_REG0 0x15E0 3205072188aSJason Jin #define GUI_SCRATCH_REG0 0x15E0 3215072188aSJason Jin #define SCRATCH_REG1 0x15E4 3225072188aSJason Jin #define GUI_SCRATCH_REG1 0x15E4 3235072188aSJason Jin #define SCRATCH_REG2 0x15E8 3245072188aSJason Jin #define GUI_SCRATCH_REG2 0x15E8 3255072188aSJason Jin #define SCRATCH_REG3 0x15EC 3265072188aSJason Jin #define GUI_SCRATCH_REG3 0x15EC 3275072188aSJason Jin #define SCRATCH_REG4 0x15F0 3285072188aSJason Jin #define GUI_SCRATCH_REG4 0x15F0 3295072188aSJason Jin #define SCRATCH_REG5 0x15F4 3305072188aSJason Jin #define GUI_SCRATCH_REG5 0x15F4 3315072188aSJason Jin #define SCRATCH_UMSK 0x0770 3325072188aSJason Jin #define SCRATCH_ADDR 0x0774 3335072188aSJason Jin #define DP_BRUSH_FRGD_CLR 0x147C 3345072188aSJason Jin #define DP_BRUSH_BKGD_CLR 0x1478 3355072188aSJason Jin #define DST_LINE_START 0x1600 3365072188aSJason Jin #define DST_LINE_END 0x1604 3375072188aSJason Jin #define SRC_OFFSET 0x15AC 3385072188aSJason Jin #define SRC_PITCH 0x15B0 3395072188aSJason Jin #define SRC_TILE 0x1704 3405072188aSJason Jin #define SRC_PITCH_OFFSET 0x1428 3415072188aSJason Jin #define SRC_X 0x1414 3425072188aSJason Jin #define SRC_Y 0x1418 3435072188aSJason Jin #define SRC_X_Y 0x1590 3445072188aSJason Jin #define SRC_Y_X 0x1434 3455072188aSJason Jin #define DST_Y_X 0x1438 3465072188aSJason Jin #define DST_WIDTH_HEIGHT 0x1598 3475072188aSJason Jin #define DST_HEIGHT_WIDTH 0x143c 3485072188aSJason Jin #define DST_OFFSET 0x1404 3495072188aSJason Jin #define SRC_CLUT_ADDRESS 0x1780 3505072188aSJason Jin #define SRC_CLUT_DATA 0x1784 3515072188aSJason Jin #define SRC_CLUT_DATA_RD 0x1788 3525072188aSJason Jin #define HOST_DATA0 0x17C0 3535072188aSJason Jin #define HOST_DATA1 0x17C4 3545072188aSJason Jin #define HOST_DATA2 0x17C8 3555072188aSJason Jin #define HOST_DATA3 0x17CC 3565072188aSJason Jin #define HOST_DATA4 0x17D0 3575072188aSJason Jin #define HOST_DATA5 0x17D4 3585072188aSJason Jin #define HOST_DATA6 0x17D8 3595072188aSJason Jin #define HOST_DATA7 0x17DC 3605072188aSJason Jin #define HOST_DATA_LAST 0x17E0 3615072188aSJason Jin #define DP_SRC_ENDIAN 0x15D4 3625072188aSJason Jin #define DP_SRC_FRGD_CLR 0x15D8 3635072188aSJason Jin #define DP_SRC_BKGD_CLR 0x15DC 3645072188aSJason Jin #define SC_LEFT 0x1640 3655072188aSJason Jin #define SC_RIGHT 0x1644 3665072188aSJason Jin #define SC_TOP 0x1648 3675072188aSJason Jin #define SC_BOTTOM 0x164C 3685072188aSJason Jin #define SRC_SC_RIGHT 0x1654 3695072188aSJason Jin #define SRC_SC_BOTTOM 0x165C 3705072188aSJason Jin #define DP_CNTL 0x16C0 3715072188aSJason Jin #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 3725072188aSJason Jin #define DP_DATATYPE 0x16C4 3735072188aSJason Jin #define DP_MIX 0x16C8 3745072188aSJason Jin #define DP_WRITE_MSK 0x16CC 3755072188aSJason Jin #define DP_XOP 0x17F8 3765072188aSJason Jin #define CLR_CMP_CLR_SRC 0x15C4 3775072188aSJason Jin #define CLR_CMP_CLR_DST 0x15C8 3785072188aSJason Jin #define CLR_CMP_CNTL 0x15C0 3795072188aSJason Jin #define CLR_CMP_MSK 0x15CC 3805072188aSJason Jin #define DSTCACHE_MODE 0x1710 3815072188aSJason Jin #define DSTCACHE_CTLSTAT 0x1714 3825072188aSJason Jin #define DEFAULT_PITCH_OFFSET 0x16E0 3835072188aSJason Jin #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 3845072188aSJason Jin #define DEFAULT_SC_TOP_LEFT 0x16EC 3855072188aSJason Jin #define SRC_PITCH_OFFSET 0x1428 3865072188aSJason Jin #define DST_PITCH_OFFSET 0x142C 3875072188aSJason Jin #define DP_GUI_MASTER_CNTL 0x146C 3885072188aSJason Jin #define SC_TOP_LEFT 0x16EC 3895072188aSJason Jin #define SC_BOTTOM_RIGHT 0x16F0 3905072188aSJason Jin #define SRC_SC_BOTTOM_RIGHT 0x16F4 3915072188aSJason Jin #define RB2D_DSTCACHE_MODE 0x3428 3925072188aSJason Jin #define RB2D_DSTCACHE_CTLSTAT 0x342C 3935072188aSJason Jin #define LVDS_GEN_CNTL 0x02d0 3945072188aSJason Jin #define LVDS_PLL_CNTL 0x02d4 3955072188aSJason Jin #define FP2_GEN_CNTL 0x0288 3965072188aSJason Jin #define TMDS_CNTL 0x0294 3975072188aSJason Jin #define TMDS_CRC 0x02a0 3985072188aSJason Jin #define TMDS_TRANSMITTER_CNTL 0x02a4 3995072188aSJason Jin #define MPP_TB_CONFIG 0x01c0 4005072188aSJason Jin #define PAMAC0_DLY_CNTL 0x0a94 4015072188aSJason Jin #define PAMAC1_DLY_CNTL 0x0a98 4025072188aSJason Jin #define PAMAC2_DLY_CNTL 0x0a9c 4035072188aSJason Jin #define FW_CNTL 0x0118 4045072188aSJason Jin #define FCP_CNTL 0x0910 4055072188aSJason Jin #define VGA_DDA_ON_OFF 0x02ec 4065072188aSJason Jin #define TV_MASTER_CNTL 0x0800 4075072188aSJason Jin 4089c7e4b06SWolfgang Denk /* #define BASE_CODE 0x0f0b */ 4095072188aSJason Jin #define BIOS_0_SCRATCH 0x0010 4105072188aSJason Jin #define BIOS_1_SCRATCH 0x0014 4115072188aSJason Jin #define BIOS_2_SCRATCH 0x0018 4125072188aSJason Jin #define BIOS_3_SCRATCH 0x001c 4135072188aSJason Jin #define BIOS_4_SCRATCH 0x0020 4145072188aSJason Jin #define BIOS_5_SCRATCH 0x0024 4155072188aSJason Jin #define BIOS_6_SCRATCH 0x0028 4165072188aSJason Jin #define BIOS_7_SCRATCH 0x002c 4175072188aSJason Jin 4185072188aSJason Jin #define HDP_SOFT_RESET (1 << 26) 4195072188aSJason Jin 4205072188aSJason Jin #define TV_DAC_CNTL 0x088c 4215072188aSJason Jin #define GPIOPAD_MASK 0x0198 4225072188aSJason Jin #define GPIOPAD_A 0x019c 4235072188aSJason Jin #define GPIOPAD_EN 0x01a0 4245072188aSJason Jin #define GPIOPAD_Y 0x01a4 4255072188aSJason Jin #define ZV_LCDPAD_MASK 0x01a8 4265072188aSJason Jin #define ZV_LCDPAD_A 0x01ac 4275072188aSJason Jin #define ZV_LCDPAD_EN 0x01b0 4285072188aSJason Jin #define ZV_LCDPAD_Y 0x01b4 4295072188aSJason Jin 4305072188aSJason Jin /* PLL Registers */ 4315072188aSJason Jin #define CLK_PIN_CNTL 0x0001 4325072188aSJason Jin #define PPLL_CNTL 0x0002 4335072188aSJason Jin #define PPLL_REF_DIV 0x0003 4345072188aSJason Jin #define PPLL_DIV_0 0x0004 4355072188aSJason Jin #define PPLL_DIV_1 0x0005 4365072188aSJason Jin #define PPLL_DIV_2 0x0006 4375072188aSJason Jin #define PPLL_DIV_3 0x0007 4385072188aSJason Jin #define VCLK_ECP_CNTL 0x0008 4395072188aSJason Jin #define HTOTAL_CNTL 0x0009 4405072188aSJason Jin #define M_SPLL_REF_FB_DIV 0x000a 4415072188aSJason Jin #define AGP_PLL_CNTL 0x000b 4425072188aSJason Jin #define SPLL_CNTL 0x000c 4435072188aSJason Jin #define SCLK_CNTL 0x000d 4445072188aSJason Jin #define MPLL_CNTL 0x000e 4455072188aSJason Jin #define MDLL_CKO 0x000f 4465072188aSJason Jin #define MDLL_RDCKA 0x0010 4475072188aSJason Jin #define MCLK_CNTL 0x0012 4485072188aSJason Jin #define AGP_PLL_CNTL 0x000b 4495072188aSJason Jin #define PLL_TEST_CNTL 0x0013 4505072188aSJason Jin #define CLK_PWRMGT_CNTL 0x0014 4515072188aSJason Jin #define PLL_PWRMGT_CNTL 0x0015 4525072188aSJason Jin #define MCLK_MISC 0x001f 4535072188aSJason Jin #define P2PLL_CNTL 0x002a 4545072188aSJason Jin #define P2PLL_REF_DIV 0x002b 4555072188aSJason Jin #define PIXCLKS_CNTL 0x002d 4565072188aSJason Jin #define SCLK_MORE_CNTL 0x0035 4575072188aSJason Jin 4585072188aSJason Jin /* MCLK_CNTL bit constants */ 4595072188aSJason Jin #define FORCEON_MCLKA (1 << 16) 4605072188aSJason Jin #define FORCEON_MCLKB (1 << 17) 4615072188aSJason Jin #define FORCEON_YCLKA (1 << 18) 4625072188aSJason Jin #define FORCEON_YCLKB (1 << 19) 4635072188aSJason Jin #define FORCEON_MC (1 << 20) 4645072188aSJason Jin #define FORCEON_AIC (1 << 21) 4655072188aSJason Jin 4665072188aSJason Jin /* SCLK_CNTL bit constants */ 4675072188aSJason Jin #define DYN_STOP_LAT_MASK 0x00007ff8 4685072188aSJason Jin #define CP_MAX_DYN_STOP_LAT 0x0008 4695072188aSJason Jin #define SCLK_FORCEON_MASK 0xffff8000 4705072188aSJason Jin 4715072188aSJason Jin /* SCLK_MORE_CNTL bit constants */ 4725072188aSJason Jin #define SCLK_MORE_FORCEON 0x0700 4735072188aSJason Jin 4745072188aSJason Jin /* BUS_CNTL bit constants */ 4755072188aSJason Jin #define BUS_DBL_RESYNC 0x00000001 4765072188aSJason Jin #define BUS_MSTR_RESET 0x00000002 4775072188aSJason Jin #define BUS_FLUSH_BUF 0x00000004 4785072188aSJason Jin #define BUS_STOP_REQ_DIS 0x00000008 4795072188aSJason Jin #define BUS_ROTATION_DIS 0x00000010 4805072188aSJason Jin #define BUS_MASTER_DIS 0x00000040 4815072188aSJason Jin #define BUS_ROM_WRT_EN 0x00000080 4825072188aSJason Jin #define BUS_DIS_ROM 0x00001000 4835072188aSJason Jin #define BUS_PCI_READ_RETRY_EN 0x00002000 4845072188aSJason Jin #define BUS_AGP_AD_STEPPING_EN 0x00004000 4855072188aSJason Jin #define BUS_PCI_WRT_RETRY_EN 0x00008000 4865072188aSJason Jin #define BUS_MSTR_RD_MULT 0x00100000 4875072188aSJason Jin #define BUS_MSTR_RD_LINE 0x00200000 4885072188aSJason Jin #define BUS_SUSPEND 0x00400000 4895072188aSJason Jin #define LAT_16X 0x00800000 4905072188aSJason Jin #define BUS_RD_DISCARD_EN 0x01000000 4915072188aSJason Jin #define BUS_RD_ABORT_EN 0x02000000 4925072188aSJason Jin #define BUS_MSTR_WS 0x04000000 4935072188aSJason Jin #define BUS_PARKING_DIS 0x08000000 4945072188aSJason Jin #define BUS_MSTR_DISCONNECT_EN 0x10000000 4955072188aSJason Jin #define BUS_WRT_BURST 0x20000000 4965072188aSJason Jin #define BUS_READ_BURST 0x40000000 4975072188aSJason Jin #define BUS_RDY_READ_DLY 0x80000000 4985072188aSJason Jin 4995072188aSJason Jin /* PIXCLKS_CNTL */ 5005072188aSJason Jin #define PIX2CLK_SRC_SEL_MASK 0x03 5015072188aSJason Jin #define PIX2CLK_SRC_SEL_CPUCLK 0x00 5025072188aSJason Jin #define PIX2CLK_SRC_SEL_PSCANCLK 0x01 5035072188aSJason Jin #define PIX2CLK_SRC_SEL_BYTECLK 0x02 5045072188aSJason Jin #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 5055072188aSJason Jin #define PIX2CLK_ALWAYS_ONb (1<<6) 5065072188aSJason Jin #define PIX2CLK_DAC_ALWAYS_ONb (1<<7) 5075072188aSJason Jin #define PIXCLK_TV_SRC_SEL (1 << 8) 5085072188aSJason Jin #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 5095072188aSJason Jin #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 5105072188aSJason Jin 5115072188aSJason Jin 5125072188aSJason Jin /* CLOCK_CNTL_INDEX bit constants */ 5135072188aSJason Jin #define PLL_WR_EN 0x00000080 5145072188aSJason Jin 5155072188aSJason Jin /* CONFIG_CNTL bit constants */ 516*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VGA_RAM_EN 0x00000100 517*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16) 518*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATI_REV_A11 (0 << 16) 519*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATI_REV_A12 (1 << 16) 520*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATI_REV_A13 (2 << 16) 5215072188aSJason Jin 5225072188aSJason Jin /* CRTC_EXT_CNTL bit constants */ 5235072188aSJason Jin #define VGA_ATI_LINEAR 0x00000008 5245072188aSJason Jin #define VGA_128KAP_PAGING 0x00000010 5255072188aSJason Jin #define XCRT_CNT_EN (1 << 6) 5265072188aSJason Jin #define CRTC_HSYNC_DIS (1 << 8) 5275072188aSJason Jin #define CRTC_VSYNC_DIS (1 << 9) 5285072188aSJason Jin #define CRTC_DISPLAY_DIS (1 << 10) 5295072188aSJason Jin #define CRTC_CRT_ON (1 << 15) 5305072188aSJason Jin 5315072188aSJason Jin 5325072188aSJason Jin /* DSTCACHE_CTLSTAT bit constants */ 5335072188aSJason Jin #define RB2D_DC_FLUSH (3 << 0) 5345072188aSJason Jin #define RB2D_DC_FLUSH_ALL 0xf 5355072188aSJason Jin #define RB2D_DC_BUSY (1 << 31) 5365072188aSJason Jin 5375072188aSJason Jin 5385072188aSJason Jin /* CRTC_GEN_CNTL bit constants */ 5395072188aSJason Jin #define CRTC_DBL_SCAN_EN 0x00000001 5405072188aSJason Jin #define CRTC_CUR_EN 0x00010000 5415072188aSJason Jin #define CRTC_INTERLACE_EN (1 << 1) 5425072188aSJason Jin #define CRTC_BYPASS_LUT_EN (1 << 14) 5435072188aSJason Jin #define CRTC_EXT_DISP_EN (1 << 24) 5445072188aSJason Jin #define CRTC_EN (1 << 25) 5455072188aSJason Jin #define CRTC_DISP_REQ_EN_B (1 << 26) 5465072188aSJason Jin 5475072188aSJason Jin /* CRTC_STATUS bit constants */ 5485072188aSJason Jin #define CRTC_VBLANK 0x00000001 5495072188aSJason Jin 5505072188aSJason Jin /* CRTC2_GEN_CNTL bit constants */ 5515072188aSJason Jin #define CRT2_ON (1 << 7) 5525072188aSJason Jin #define CRTC2_DISPLAY_DIS (1 << 23) 5535072188aSJason Jin #define CRTC2_EN (1 << 25) 5545072188aSJason Jin #define CRTC2_DISP_REQ_EN_B (1 << 26) 5555072188aSJason Jin 5565072188aSJason Jin /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ 5575072188aSJason Jin #define CUR_LOCK 0x80000000 5585072188aSJason Jin 5595072188aSJason Jin /* GPIO bit constants */ 5605072188aSJason Jin #define GPIO_A_0 (1 << 0) 5615072188aSJason Jin #define GPIO_A_1 (1 << 1) 5625072188aSJason Jin #define GPIO_Y_0 (1 << 8) 5635072188aSJason Jin #define GPIO_Y_1 (1 << 9) 5645072188aSJason Jin #define GPIO_EN_0 (1 << 16) 5655072188aSJason Jin #define GPIO_EN_1 (1 << 17) 5665072188aSJason Jin #define GPIO_MASK_0 (1 << 24) 5675072188aSJason Jin #define GPIO_MASK_1 (1 << 25) 5685072188aSJason Jin #define VGA_DDC_DATA_OUTPUT GPIO_A_0 5695072188aSJason Jin #define VGA_DDC_CLK_OUTPUT GPIO_A_1 5705072188aSJason Jin #define VGA_DDC_DATA_INPUT GPIO_Y_0 5715072188aSJason Jin #define VGA_DDC_CLK_INPUT GPIO_Y_1 5725072188aSJason Jin #define VGA_DDC_DATA_OUT_EN GPIO_EN_0 5735072188aSJason Jin #define VGA_DDC_CLK_OUT_EN GPIO_EN_1 5745072188aSJason Jin 5755072188aSJason Jin 5765072188aSJason Jin /* FP bit constants */ 5779c7e4b06SWolfgang Denk #define FP_CRTC_H_TOTAL_MASK 000003ff 5785072188aSJason Jin #define FP_CRTC_H_DISP_MASK 0x01ff0000 5795072188aSJason Jin #define FP_CRTC_V_TOTAL_MASK 0x00000fff 5805072188aSJason Jin #define FP_CRTC_V_DISP_MASK 0x0fff0000 5815072188aSJason Jin #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 5825072188aSJason Jin #define FP_H_SYNC_WID_MASK 0x003f0000 5835072188aSJason Jin #define FP_V_SYNC_STRT_MASK 0x00000fff 5845072188aSJason Jin #define FP_V_SYNC_WID_MASK 0x001f0000 5855072188aSJason Jin #define FP_CRTC_H_TOTAL_SHIFT 0x00000000 5865072188aSJason Jin #define FP_CRTC_H_DISP_SHIFT 0x00000010 5875072188aSJason Jin #define FP_CRTC_V_TOTAL_SHIFT 0x00000000 5885072188aSJason Jin #define FP_CRTC_V_DISP_SHIFT 0x00000010 5895072188aSJason Jin #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 5905072188aSJason Jin #define FP_H_SYNC_WID_SHIFT 0x00000010 5915072188aSJason Jin #define FP_V_SYNC_STRT_SHIFT 0x00000000 5925072188aSJason Jin #define FP_V_SYNC_WID_SHIFT 0x00000010 5935072188aSJason Jin 5945072188aSJason Jin /* FP_GEN_CNTL bit constants */ 5955072188aSJason Jin #define FP_FPON (1 << 0) 5965072188aSJason Jin #define FP_TMDS_EN (1 << 2) 5975072188aSJason Jin #define FP_PANEL_FORMAT (1 << 3) 5985072188aSJason Jin #define FP_EN_TMDS (1 << 7) 5995072188aSJason Jin #define FP_DETECT_SENSE (1 << 8) 6005072188aSJason Jin #define R200_FP_SOURCE_SEL_MASK (3 << 10) 6015072188aSJason Jin #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) 6025072188aSJason Jin #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) 6035072188aSJason Jin #define R200_FP_SOURCE_SEL_RMX (2 << 10) 6045072188aSJason Jin #define R200_FP_SOURCE_SEL_TRANS (3 << 10) 6055072188aSJason Jin #define FP_SEL_CRTC1 (0 << 13) 6065072188aSJason Jin #define FP_SEL_CRTC2 (1 << 13) 6075072188aSJason Jin #define FP_USE_VGA_HSYNC (1 << 14) 6085072188aSJason Jin #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 6095072188aSJason Jin #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 6105072188aSJason Jin #define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 6115072188aSJason Jin #define FP_CRTC_USE_SHADOW_VEND (1 << 18) 6125072188aSJason Jin #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 6135072188aSJason Jin #define FP_DFP_SYNC_SEL (1 << 21) 6145072188aSJason Jin #define FP_CRTC_LOCK_8DOT (1 << 22) 6155072188aSJason Jin #define FP_CRT_SYNC_SEL (1 << 23) 6165072188aSJason Jin #define FP_USE_SHADOW_EN (1 << 24) 6175072188aSJason Jin #define FP_CRT_SYNC_ALT (1 << 26) 6185072188aSJason Jin 6195072188aSJason Jin /* FP2_GEN_CNTL bit constants */ 6205072188aSJason Jin #define FP2_BLANK_EN (1 << 1) 6215072188aSJason Jin #define FP2_ON (1 << 2) 6225072188aSJason Jin #define FP2_PANEL_FORMAT (1 << 3) 6235072188aSJason Jin #define FP2_SOURCE_SEL_MASK (3 << 10) 6245072188aSJason Jin #define FP2_SOURCE_SEL_CRTC2 (1 << 10) 6255072188aSJason Jin #define FP2_SRC_SEL_MASK (3 << 13) 6265072188aSJason Jin #define FP2_SRC_SEL_CRTC2 (1 << 13) 6275072188aSJason Jin #define FP2_FP_POL (1 << 16) 6285072188aSJason Jin #define FP2_LP_POL (1 << 17) 6295072188aSJason Jin #define FP2_SCK_POL (1 << 18) 6305072188aSJason Jin #define FP2_LCD_CNTL_MASK (7 << 19) 6315072188aSJason Jin #define FP2_PAD_FLOP_EN (1 << 22) 6325072188aSJason Jin #define FP2_CRC_EN (1 << 23) 6335072188aSJason Jin #define FP2_CRC_READ_EN (1 << 24) 6345072188aSJason Jin #define FP2_DV0_EN (1 << 25) 6355072188aSJason Jin #define FP2_DV0_RATE_SEL_SDR (1 << 26) 6365072188aSJason Jin 6375072188aSJason Jin 6385072188aSJason Jin /* LVDS_GEN_CNTL bit constants */ 6395072188aSJason Jin #define LVDS_ON (1 << 0) 6405072188aSJason Jin #define LVDS_DISPLAY_DIS (1 << 1) 6415072188aSJason Jin #define LVDS_PANEL_TYPE (1 << 2) 6425072188aSJason Jin #define LVDS_PANEL_FORMAT (1 << 3) 6435072188aSJason Jin #define LVDS_EN (1 << 7) 6445072188aSJason Jin #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 6455072188aSJason Jin #define LVDS_BL_MOD_LEVEL_SHIFT 8 6465072188aSJason Jin #define LVDS_BL_MOD_EN (1 << 16) 6475072188aSJason Jin #define LVDS_DIGON (1 << 18) 6485072188aSJason Jin #define LVDS_BLON (1 << 19) 6495072188aSJason Jin #define LVDS_SEL_CRTC2 (1 << 23) 6505072188aSJason Jin #define LVDS_STATE_MASK \ 6515072188aSJason Jin (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) 6525072188aSJason Jin 6535072188aSJason Jin /* LVDS_PLL_CNTL bit constatns */ 6545072188aSJason Jin #define HSYNC_DELAY_SHIFT 0x1c 6555072188aSJason Jin #define HSYNC_DELAY_MASK (0xf << 0x1c) 6565072188aSJason Jin 6575072188aSJason Jin /* TMDS_TRANSMITTER_CNTL bit constants */ 6585072188aSJason Jin #define TMDS_PLL_EN (1 << 0) 6595072188aSJason Jin #define TMDS_PLLRST (1 << 1) 6605072188aSJason Jin #define TMDS_RAN_PAT_RST (1 << 7) 6615072188aSJason Jin #define TMDS_ICHCSEL (1 << 28) 6625072188aSJason Jin 6635072188aSJason Jin /* FP_HORZ_STRETCH bit constants */ 6645072188aSJason Jin #define HORZ_STRETCH_RATIO_MASK 0xffff 6655072188aSJason Jin #define HORZ_STRETCH_RATIO_MAX 4096 6665072188aSJason Jin #define HORZ_PANEL_SIZE (0x1ff << 16) 6675072188aSJason Jin #define HORZ_PANEL_SHIFT 16 6685072188aSJason Jin #define HORZ_STRETCH_PIXREP (0 << 25) 6695072188aSJason Jin #define HORZ_STRETCH_BLEND (1 << 26) 6705072188aSJason Jin #define HORZ_STRETCH_ENABLE (1 << 25) 6715072188aSJason Jin #define HORZ_AUTO_RATIO (1 << 27) 6725072188aSJason Jin #define HORZ_FP_LOOP_STRETCH (0x7 << 28) 6735072188aSJason Jin #define HORZ_AUTO_RATIO_INC (1 << 31) 6745072188aSJason Jin 6755072188aSJason Jin 6765072188aSJason Jin /* FP_VERT_STRETCH bit constants */ 6775072188aSJason Jin #define VERT_STRETCH_RATIO_MASK 0xfff 6785072188aSJason Jin #define VERT_STRETCH_RATIO_MAX 4096 6795072188aSJason Jin #define VERT_PANEL_SIZE (0xfff << 12) 6805072188aSJason Jin #define VERT_PANEL_SHIFT 12 6815072188aSJason Jin #define VERT_STRETCH_LINREP (0 << 26) 6825072188aSJason Jin #define VERT_STRETCH_BLEND (1 << 26) 6835072188aSJason Jin #define VERT_STRETCH_ENABLE (1 << 25) 6845072188aSJason Jin #define VERT_AUTO_RATIO_EN (1 << 27) 6855072188aSJason Jin #define VERT_FP_LOOP_STRETCH (0x7 << 28) 6865072188aSJason Jin #define VERT_STRETCH_RESERVED 0xf1000000 6875072188aSJason Jin 6885072188aSJason Jin /* DAC_CNTL bit constants */ 6895072188aSJason Jin #define DAC_8BIT_EN 0x00000100 6905072188aSJason Jin #define DAC_4BPP_PIX_ORDER 0x00000200 6915072188aSJason Jin #define DAC_CRC_EN 0x00080000 6925072188aSJason Jin #define DAC_MASK_ALL (0xff << 24) 6935072188aSJason Jin #define DAC_PDWN (1 << 15) 6945072188aSJason Jin #define DAC_EXPAND_MODE (1 << 14) 6955072188aSJason Jin #define DAC_VGA_ADR_EN (1 << 13) 6965072188aSJason Jin #define DAC_RANGE_CNTL (3 << 0) 6975072188aSJason Jin #define DAC_RANGE_CNTL_MASK 0x03 6985072188aSJason Jin #define DAC_BLANKING (1 << 2) 6995072188aSJason Jin #define DAC_CMP_EN (1 << 3) 7005072188aSJason Jin #define DAC_CMP_OUTPUT (1 << 7) 7015072188aSJason Jin 7025072188aSJason Jin /* DAC_CNTL2 bit constants */ 7035072188aSJason Jin #define DAC2_EXPAND_MODE (1 << 14) 7045072188aSJason Jin #define DAC2_CMP_EN (1 << 7) 7055072188aSJason Jin #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) 7065072188aSJason Jin 7075072188aSJason Jin /* DAC_EXT_CNTL bit constants */ 7085072188aSJason Jin #define DAC_FORCE_BLANK_OFF_EN (1 << 4) 7095072188aSJason Jin #define DAC_FORCE_DATA_EN (1 << 5) 7105072188aSJason Jin #define DAC_FORCE_DATA_SEL_MASK (3 << 6) 7115072188aSJason Jin #define DAC_FORCE_DATA_MASK 0x0003ff00 7125072188aSJason Jin #define DAC_FORCE_DATA_SHIFT 8 7135072188aSJason Jin 7145072188aSJason Jin /* GEN_RESET_CNTL bit constants */ 7155072188aSJason Jin #define SOFT_RESET_GUI 0x00000001 7165072188aSJason Jin #define SOFT_RESET_VCLK 0x00000100 7175072188aSJason Jin #define SOFT_RESET_PCLK 0x00000200 7185072188aSJason Jin #define SOFT_RESET_ECP 0x00000400 7195072188aSJason Jin #define SOFT_RESET_DISPENG_XCLK 0x00000800 7205072188aSJason Jin 7215072188aSJason Jin /* MEM_CNTL bit constants */ 7225072188aSJason Jin #define MEM_CTLR_STATUS_IDLE 0x00000000 7235072188aSJason Jin #define MEM_CTLR_STATUS_BUSY 0x00100000 7245072188aSJason Jin #define MEM_SEQNCR_STATUS_IDLE 0x00000000 7255072188aSJason Jin #define MEM_SEQNCR_STATUS_BUSY 0x00200000 7265072188aSJason Jin #define MEM_ARBITER_STATUS_IDLE 0x00000000 7275072188aSJason Jin #define MEM_ARBITER_STATUS_BUSY 0x00400000 7285072188aSJason Jin #define MEM_REQ_UNLOCK 0x00000000 7295072188aSJason Jin #define MEM_REQ_LOCK 0x00800000 7305072188aSJason Jin #define MEM_NUM_CHANNELS_MASK 0x00000001 7315072188aSJason Jin #define MEM_USE_B_CH_ONLY 0x00000002 7325072188aSJason Jin #define RV100_MEM_HALF_MODE 0x00000008 7335072188aSJason Jin #define R300_MEM_NUM_CHANNELS_MASK 0x00000003 7345072188aSJason Jin #define R300_MEM_USE_CD_CH_ONLY 0x00000004 7355072188aSJason Jin 7365072188aSJason Jin 7375072188aSJason Jin /* RBBM_SOFT_RESET bit constants */ 7385072188aSJason Jin #define SOFT_RESET_CP (1 << 0) 7395072188aSJason Jin #define SOFT_RESET_HI (1 << 1) 7405072188aSJason Jin #define SOFT_RESET_SE (1 << 2) 7415072188aSJason Jin #define SOFT_RESET_RE (1 << 3) 7425072188aSJason Jin #define SOFT_RESET_PP (1 << 4) 7435072188aSJason Jin #define SOFT_RESET_E2 (1 << 5) 7445072188aSJason Jin #define SOFT_RESET_RB (1 << 6) 7455072188aSJason Jin #define SOFT_RESET_HDP (1 << 7) 7465072188aSJason Jin 7475072188aSJason Jin /* SURFACE_CNTL bit consants */ 7485072188aSJason Jin #define SURF_TRANSLATION_DIS (1 << 8) 7495072188aSJason Jin #define NONSURF_AP0_SWP_16BPP (1 << 20) 7505072188aSJason Jin #define NONSURF_AP0_SWP_32BPP (1 << 21) 7515072188aSJason Jin #define NONSURF_AP1_SWP_16BPP (1 << 22) 7525072188aSJason Jin #define NONSURF_AP1_SWP_32BPP (1 << 23) 7535072188aSJason Jin 7541b8607e1SAnatolij Gustschin #define R200_SURF_TILE_COLOR_MACRO (1 << 16) 7551b8607e1SAnatolij Gustschin 7565072188aSJason Jin /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ 7575072188aSJason Jin #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 7585072188aSJason Jin #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 7595072188aSJason Jin 7605072188aSJason Jin /* MM_INDEX bit constants */ 7615072188aSJason Jin #define MM_APER 0x80000000 7625072188aSJason Jin 7635072188aSJason Jin /* CLR_CMP_CNTL bit constants */ 7645072188aSJason Jin #define COMPARE_SRC_FALSE 0x00000000 7655072188aSJason Jin #define COMPARE_SRC_TRUE 0x00000001 7665072188aSJason Jin #define COMPARE_SRC_NOT_EQUAL 0x00000004 7675072188aSJason Jin #define COMPARE_SRC_EQUAL 0x00000005 7685072188aSJason Jin #define COMPARE_SRC_EQUAL_FLIP 0x00000007 7695072188aSJason Jin #define COMPARE_DST_FALSE 0x00000000 7705072188aSJason Jin #define COMPARE_DST_TRUE 0x00000100 7715072188aSJason Jin #define COMPARE_DST_NOT_EQUAL 0x00000400 7725072188aSJason Jin #define COMPARE_DST_EQUAL 0x00000500 7735072188aSJason Jin #define COMPARE_DESTINATION 0x00000000 7745072188aSJason Jin #define COMPARE_SOURCE 0x01000000 7755072188aSJason Jin #define COMPARE_SRC_AND_DST 0x02000000 7765072188aSJason Jin 7775072188aSJason Jin 7785072188aSJason Jin /* DP_CNTL bit constants */ 7795072188aSJason Jin #define DST_X_RIGHT_TO_LEFT 0x00000000 7805072188aSJason Jin #define DST_X_LEFT_TO_RIGHT 0x00000001 7815072188aSJason Jin #define DST_Y_BOTTOM_TO_TOP 0x00000000 7825072188aSJason Jin #define DST_Y_TOP_TO_BOTTOM 0x00000002 7835072188aSJason Jin #define DST_X_MAJOR 0x00000000 7845072188aSJason Jin #define DST_Y_MAJOR 0x00000004 7855072188aSJason Jin #define DST_X_TILE 0x00000008 7865072188aSJason Jin #define DST_Y_TILE 0x00000010 7875072188aSJason Jin #define DST_LAST_PEL 0x00000020 7885072188aSJason Jin #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 7895072188aSJason Jin #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 7905072188aSJason Jin #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 7915072188aSJason Jin #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 7925072188aSJason Jin #define DST_BRES_SIGN 0x00000100 7935072188aSJason Jin #define DST_HOST_BIG_ENDIAN_EN 0x00000200 7945072188aSJason Jin #define DST_POLYLINE_NONLAST 0x00008000 7955072188aSJason Jin #define DST_RASTER_STALL 0x00010000 7965072188aSJason Jin #define DST_POLY_EDGE 0x00040000 7975072188aSJason Jin 7985072188aSJason Jin 7995072188aSJason Jin /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ 8005072188aSJason Jin #define DST_X_MAJOR_S 0x00000000 8015072188aSJason Jin #define DST_Y_MAJOR_S 0x00000001 8025072188aSJason Jin #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 8035072188aSJason Jin #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 8045072188aSJason Jin #define DST_X_RIGHT_TO_LEFT_S 0x00000000 8055072188aSJason Jin #define DST_X_LEFT_TO_RIGHT_S 0x80000000 8065072188aSJason Jin 8075072188aSJason Jin 8085072188aSJason Jin /* DP_DATATYPE bit constants */ 8095072188aSJason Jin #define DST_8BPP 0x00000002 8105072188aSJason Jin #define DST_15BPP 0x00000003 8115072188aSJason Jin #define DST_16BPP 0x00000004 8125072188aSJason Jin #define DST_24BPP 0x00000005 8135072188aSJason Jin #define DST_32BPP 0x00000006 8145072188aSJason Jin #define DST_8BPP_RGB332 0x00000007 8155072188aSJason Jin #define DST_8BPP_Y8 0x00000008 8165072188aSJason Jin #define DST_8BPP_RGB8 0x00000009 8175072188aSJason Jin #define DST_16BPP_VYUY422 0x0000000b 8185072188aSJason Jin #define DST_16BPP_YVYU422 0x0000000c 8195072188aSJason Jin #define DST_32BPP_AYUV444 0x0000000e 8205072188aSJason Jin #define DST_16BPP_ARGB4444 0x0000000f 8215072188aSJason Jin #define BRUSH_SOLIDCOLOR 0x00000d00 8225072188aSJason Jin #define SRC_MONO 0x00000000 8235072188aSJason Jin #define SRC_MONO_LBKGD 0x00010000 8245072188aSJason Jin #define SRC_DSTCOLOR 0x00030000 8255072188aSJason Jin #define BYTE_ORDER_MSB_TO_LSB 0x00000000 8265072188aSJason Jin #define BYTE_ORDER_LSB_TO_MSB 0x40000000 8275072188aSJason Jin #define DP_CONVERSION_TEMP 0x80000000 8285072188aSJason Jin #define HOST_BIG_ENDIAN_EN (1 << 29) 8295072188aSJason Jin 8305072188aSJason Jin 8315072188aSJason Jin /* DP_GUI_MASTER_CNTL bit constants */ 8325072188aSJason Jin #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 8335072188aSJason Jin #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 8345072188aSJason Jin #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 8355072188aSJason Jin #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 8365072188aSJason Jin #define GMC_SRC_CLIP_DEFAULT 0x00000000 8375072188aSJason Jin #define GMC_SRC_CLIP_LEAVE 0x00000004 8385072188aSJason Jin #define GMC_DST_CLIP_DEFAULT 0x00000000 8395072188aSJason Jin #define GMC_DST_CLIP_LEAVE 0x00000008 8405072188aSJason Jin #define GMC_BRUSH_8x8MONO 0x00000000 8415072188aSJason Jin #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 8425072188aSJason Jin #define GMC_BRUSH_8x1MONO 0x00000020 8435072188aSJason Jin #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 8445072188aSJason Jin #define GMC_BRUSH_1x8MONO 0x00000040 8455072188aSJason Jin #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 8465072188aSJason Jin #define GMC_BRUSH_32x1MONO 0x00000060 8475072188aSJason Jin #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 8485072188aSJason Jin #define GMC_BRUSH_32x32MONO 0x00000080 8495072188aSJason Jin #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 8505072188aSJason Jin #define GMC_BRUSH_8x8COLOR 0x000000a0 8515072188aSJason Jin #define GMC_BRUSH_8x1COLOR 0x000000b0 8525072188aSJason Jin #define GMC_BRUSH_1x8COLOR 0x000000c0 8535072188aSJason Jin #define GMC_BRUSH_SOLID_COLOR 0x000000d0 8545072188aSJason Jin #define GMC_DST_8BPP 0x00000200 8555072188aSJason Jin #define GMC_DST_15BPP 0x00000300 8565072188aSJason Jin #define GMC_DST_16BPP 0x00000400 8575072188aSJason Jin #define GMC_DST_24BPP 0x00000500 8585072188aSJason Jin #define GMC_DST_32BPP 0x00000600 8595072188aSJason Jin #define GMC_DST_8BPP_RGB332 0x00000700 8605072188aSJason Jin #define GMC_DST_8BPP_Y8 0x00000800 8615072188aSJason Jin #define GMC_DST_8BPP_RGB8 0x00000900 8625072188aSJason Jin #define GMC_DST_16BPP_VYUY422 0x00000b00 8635072188aSJason Jin #define GMC_DST_16BPP_YVYU422 0x00000c00 8645072188aSJason Jin #define GMC_DST_32BPP_AYUV444 0x00000e00 8655072188aSJason Jin #define GMC_DST_16BPP_ARGB4444 0x00000f00 8665072188aSJason Jin #define GMC_SRC_MONO 0x00000000 8675072188aSJason Jin #define GMC_SRC_MONO_LBKGD 0x00001000 8685072188aSJason Jin #define GMC_SRC_DSTCOLOR 0x00003000 8695072188aSJason Jin #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 8705072188aSJason Jin #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 8715072188aSJason Jin #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 8725072188aSJason Jin #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 8735072188aSJason Jin #define GMC_DP_SRC_RECT 0x02000000 8745072188aSJason Jin #define GMC_DP_SRC_HOST 0x03000000 8755072188aSJason Jin #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 8765072188aSJason Jin #define GMC_3D_FCN_EN_CLR 0x00000000 8775072188aSJason Jin #define GMC_3D_FCN_EN_SET 0x08000000 8785072188aSJason Jin #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 8795072188aSJason Jin #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 8805072188aSJason Jin #define GMC_AUX_CLIP_LEAVE 0x00000000 8815072188aSJason Jin #define GMC_AUX_CLIP_CLEAR 0x20000000 8825072188aSJason Jin #define GMC_WRITE_MASK_LEAVE 0x00000000 8835072188aSJason Jin #define GMC_WRITE_MASK_SET 0x40000000 8845072188aSJason Jin #define GMC_CLR_CMP_CNTL_DIS (1 << 28) 8855072188aSJason Jin #define GMC_SRC_DATATYPE_COLOR (3 << 12) 8865072188aSJason Jin #define ROP3_S 0x00cc0000 8875072188aSJason Jin #define ROP3_SRCCOPY 0x00cc0000 8885072188aSJason Jin #define ROP3_P 0x00f00000 8895072188aSJason Jin #define ROP3_PATCOPY 0x00f00000 8905072188aSJason Jin #define DP_SRC_SOURCE_MASK (7 << 24) 8915072188aSJason Jin #define GMC_BRUSH_NONE (15 << 4) 8925072188aSJason Jin #define DP_SRC_SOURCE_MEMORY (2 << 24) 8935072188aSJason Jin #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 8945072188aSJason Jin 8955072188aSJason Jin /* DP_MIX bit constants */ 8965072188aSJason Jin #define DP_SRC_RECT 0x00000200 8975072188aSJason Jin #define DP_SRC_HOST 0x00000300 8985072188aSJason Jin #define DP_SRC_HOST_BYTEALIGN 0x00000400 8995072188aSJason Jin 9005072188aSJason Jin /* MPLL_CNTL bit constants */ 9015072188aSJason Jin #define MPLL_RESET 0x00000001 9025072188aSJason Jin 9035072188aSJason Jin /* MDLL_CKO bit constants */ 9045072188aSJason Jin #define MCKOA_SLEEP 0x00000001 9055072188aSJason Jin #define MCKOA_RESET 0x00000002 9065072188aSJason Jin #define MCKOA_REF_SKEW_MASK 0x00000700 9075072188aSJason Jin #define MCKOA_FB_SKEW_MASK 0x00007000 9085072188aSJason Jin 9095072188aSJason Jin /* MDLL_RDCKA bit constants */ 9105072188aSJason Jin #define MRDCKA0_SLEEP 0x00000001 9115072188aSJason Jin #define MRDCKA0_RESET 0x00000002 9125072188aSJason Jin #define MRDCKA1_SLEEP 0x00010000 9135072188aSJason Jin #define MRDCKA1_RESET 0x00020000 9145072188aSJason Jin 9155072188aSJason Jin /* VCLK_ECP_CNTL constants */ 9165072188aSJason Jin #define VCLK_SRC_SEL_MASK 0x03 9175072188aSJason Jin #define VCLK_SRC_SEL_CPUCLK 0x00 9185072188aSJason Jin #define VCLK_SRC_SEL_PSCANCLK 0x01 9195072188aSJason Jin #define VCLK_SRC_SEL_BYTECLK 0x02 9205072188aSJason Jin #define VCLK_SRC_SEL_PPLLCLK 0x03 9215072188aSJason Jin #define PIXCLK_ALWAYS_ONb 0x00000040 9225072188aSJason Jin #define PIXCLK_DAC_ALWAYS_ONb 0x00000080 9235072188aSJason Jin 9245072188aSJason Jin /* BUS_CNTL1 constants */ 9255072188aSJason Jin #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 9265072188aSJason Jin #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 9275072188aSJason Jin #define BUS_CNTL1_AGPCLK_VALID 0x80000000 9285072188aSJason Jin 9295072188aSJason Jin /* PLL_PWRMGT_CNTL constants */ 9305072188aSJason Jin #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 9315072188aSJason Jin #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 9325072188aSJason Jin #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 9335072188aSJason Jin #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 9345072188aSJason Jin #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 9355072188aSJason Jin #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 9365072188aSJason Jin #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 9375072188aSJason Jin 9385072188aSJason Jin /* TV_DAC_CNTL constants */ 9395072188aSJason Jin #define TV_DAC_CNTL_BGSLEEP 0x00000040 9405072188aSJason Jin #define TV_DAC_CNTL_DETECT 0x00000010 9415072188aSJason Jin #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 9425072188aSJason Jin #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 9435072188aSJason Jin #define TV_DAC_CNTL_BGADJ__SHIFT 16 9445072188aSJason Jin #define TV_DAC_CNTL_DACADJ__SHIFT 20 9455072188aSJason Jin #define TV_DAC_CNTL_RDACPD 0x01000000 9465072188aSJason Jin #define TV_DAC_CNTL_GDACPD 0x02000000 9475072188aSJason Jin #define TV_DAC_CNTL_BDACPD 0x04000000 9485072188aSJason Jin 9495072188aSJason Jin /* DISP_MISC_CNTL constants */ 9505072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) 9515072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) 9525072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) 9535072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) 9545072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) 9555072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) 9565072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) 9575072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) 9585072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) 9595072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) 9605072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) 9615072188aSJason Jin #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) 9625072188aSJason Jin 9635072188aSJason Jin /* DISP_PWR_MAN constants */ 9645072188aSJason Jin #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) 9655072188aSJason Jin #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) 9665072188aSJason Jin #define DISP_PWR_MAN_DISP_D3_RST (1 << 16) 9675072188aSJason Jin #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) 9685072188aSJason Jin #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) 9695072188aSJason Jin #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) 9705072188aSJason Jin #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) 9715072188aSJason Jin #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) 9725072188aSJason Jin #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) 9735072188aSJason Jin #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) 9745072188aSJason Jin #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) 9755072188aSJason Jin #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) 9765072188aSJason Jin #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) 9775072188aSJason Jin 9785072188aSJason Jin /* masks */ 9795072188aSJason Jin 9805072188aSJason Jin #define CONFIG_MEMSIZE_MASK 0x1f000000 9815072188aSJason Jin #define MEM_CFG_TYPE 0x40000000 9825072188aSJason Jin #define DST_OFFSET_MASK 0x003fffff 9835072188aSJason Jin #define DST_PITCH_MASK 0x3fc00000 9845072188aSJason Jin #define DEFAULT_TILE_MASK 0xc0000000 9855072188aSJason Jin #define PPLL_DIV_SEL_MASK 0x00000300 9865072188aSJason Jin #define PPLL_RESET 0x00000001 9875072188aSJason Jin #define PPLL_SLEEP 0x00000002 9885072188aSJason Jin #define PPLL_ATOMIC_UPDATE_EN 0x00010000 9895072188aSJason Jin #define PPLL_REF_DIV_MASK 0x000003ff 9905072188aSJason Jin #define PPLL_FB3_DIV_MASK 0x000007ff 9915072188aSJason Jin #define PPLL_POST3_DIV_MASK 0x00070000 9925072188aSJason Jin #define PPLL_ATOMIC_UPDATE_R 0x00008000 9935072188aSJason Jin #define PPLL_ATOMIC_UPDATE_W 0x00008000 9945072188aSJason Jin #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 9955072188aSJason Jin #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) 9965072188aSJason Jin #define R300_PPLL_REF_DIV_ACC_SHIFT 18 9975072188aSJason Jin 9985072188aSJason Jin #define GUI_ACTIVE 0x80000000 9995072188aSJason Jin 10005072188aSJason Jin 10015072188aSJason Jin #define MC_IND_INDEX 0x01F8 10025072188aSJason Jin #define MC_IND_DATA 0x01FC 10035072188aSJason Jin 10045072188aSJason Jin /* PAD_CTLR_STRENGTH */ 10055072188aSJason Jin #define PAD_MANUAL_OVERRIDE 0x80000000 10065072188aSJason Jin 10079c7e4b06SWolfgang Denk /* pllCLK_PIN_CNTL */ 10085072188aSJason Jin #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L 10095072188aSJason Jin #define CLK_PIN_CNTL__OSC_EN 0x00000001L 10105072188aSJason Jin #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L 10115072188aSJason Jin #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L 10125072188aSJason Jin #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L 10135072188aSJason Jin #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L 10145072188aSJason Jin #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L 10155072188aSJason Jin #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L 10165072188aSJason Jin #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L 10175072188aSJason Jin #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L 10185072188aSJason Jin #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L 10195072188aSJason Jin #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L 10205072188aSJason Jin #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L 10215072188aSJason Jin #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L 10225072188aSJason Jin #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L 10235072188aSJason Jin #define CLK_PIN_CNTL__CG_SPARE 0x00004000L 10245072188aSJason Jin #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L 10255072188aSJason Jin #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L 10265072188aSJason Jin #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L 10275072188aSJason Jin #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L 10285072188aSJason Jin #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L 10295072188aSJason Jin #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L 10305072188aSJason Jin #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L 10315072188aSJason Jin #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L 10325072188aSJason Jin 10339c7e4b06SWolfgang Denk /* pllCLK_PWRMGT_CNTL */ 10345072188aSJason Jin #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 10355072188aSJason Jin #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 10365072188aSJason Jin #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 10375072188aSJason Jin #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 10385072188aSJason Jin #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 10395072188aSJason Jin #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 10405072188aSJason Jin #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 10415072188aSJason Jin #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 10425072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 10435072188aSJason Jin #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 10445072188aSJason Jin #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a 10455072188aSJason Jin #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c 10465072188aSJason Jin #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d 10475072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f 10485072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 10495072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 10505072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 10515072188aSJason Jin #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 10525072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 10535072188aSJason Jin #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 10545072188aSJason Jin #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 10555072188aSJason Jin #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e 10565072188aSJason Jin #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f 10575072188aSJason Jin 10589c7e4b06SWolfgang Denk /* pllP2PLL_CNTL */ 10595072188aSJason Jin #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L 10605072188aSJason Jin #define P2PLL_CNTL__P2PLL_RESET 0x00000001L 10615072188aSJason Jin #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L 10625072188aSJason Jin #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L 10635072188aSJason Jin #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L 10645072188aSJason Jin #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L 10655072188aSJason Jin #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L 10665072188aSJason Jin #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L 10675072188aSJason Jin #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L 10685072188aSJason Jin #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L 10695072188aSJason Jin #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L 10705072188aSJason Jin #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L 10715072188aSJason Jin #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L 10725072188aSJason Jin #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L 10735072188aSJason Jin #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L 10745072188aSJason Jin #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L 10755072188aSJason Jin #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L 10765072188aSJason Jin #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L 10775072188aSJason Jin #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L 10785072188aSJason Jin #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L 10795072188aSJason Jin #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L 10805072188aSJason Jin #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L 10815072188aSJason Jin #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L 10825072188aSJason Jin 10839c7e4b06SWolfgang Denk /* pllPIXCLKS_CNTL */ 10845072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 10855072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 10865072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 10875072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 10885072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 10895072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 10905072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b 10915072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c 10925072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d 10935072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e 10945072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f 10955072188aSJason Jin 10965072188aSJason Jin 10979c7e4b06SWolfgang Denk /* pllPIXCLKS_CNTL */ 10985072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L 10995072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L 11005072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L 11015072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L 11025072188aSJason Jin #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L 11035072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L 11045072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L 11055072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L 11065072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L 11075072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L 11085072188aSJason Jin #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L 11095072188aSJason Jin #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) 11105072188aSJason Jin #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) 11115072188aSJason Jin #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) 11125072188aSJason Jin #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) 11135072188aSJason Jin #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) 11145072188aSJason Jin #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) 11155072188aSJason Jin #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) 11165072188aSJason Jin #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) 11175072188aSJason Jin 11185072188aSJason Jin 11199c7e4b06SWolfgang Denk /* pllP2PLL_DIV_0 */ 11205072188aSJason Jin #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL 11215072188aSJason Jin #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L 11225072188aSJason Jin #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L 11235072188aSJason Jin #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L 11245072188aSJason Jin #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L 11255072188aSJason Jin #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L 11265072188aSJason Jin 11279c7e4b06SWolfgang Denk /* pllSCLK_CNTL */ 11285072188aSJason Jin #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L 11295072188aSJason Jin #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L 11305072188aSJason Jin #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L 11315072188aSJason Jin #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L 11325072188aSJason Jin #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L 11335072188aSJason Jin #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L 11345072188aSJason Jin #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L 11355072188aSJason Jin #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L 11365072188aSJason Jin #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L 11375072188aSJason Jin #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L 11385072188aSJason Jin #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L 11395072188aSJason Jin #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L 11405072188aSJason Jin #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L 11415072188aSJason Jin #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 11425072188aSJason Jin #define SCLK_CNTL__FORCE_DISP2 0x00008000L 11435072188aSJason Jin #define SCLK_CNTL__FORCE_CP 0x00010000L 11445072188aSJason Jin #define SCLK_CNTL__FORCE_HDP 0x00020000L 11455072188aSJason Jin #define SCLK_CNTL__FORCE_DISP1 0x00040000L 11465072188aSJason Jin #define SCLK_CNTL__FORCE_TOP 0x00080000L 11475072188aSJason Jin #define SCLK_CNTL__FORCE_E2 0x00100000L 11485072188aSJason Jin #define SCLK_CNTL__FORCE_SE 0x00200000L 11495072188aSJason Jin #define SCLK_CNTL__FORCE_IDCT 0x00400000L 11505072188aSJason Jin #define SCLK_CNTL__FORCE_VIP 0x00800000L 11515072188aSJason Jin #define SCLK_CNTL__FORCE_RE 0x01000000L 11525072188aSJason Jin #define SCLK_CNTL__FORCE_PB 0x02000000L 11535072188aSJason Jin #define SCLK_CNTL__FORCE_TAM 0x04000000L 11545072188aSJason Jin #define SCLK_CNTL__FORCE_TDM 0x08000000L 11555072188aSJason Jin #define SCLK_CNTL__FORCE_RB 0x10000000L 11565072188aSJason Jin #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L 11575072188aSJason Jin #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L 11585072188aSJason Jin #define SCLK_CNTL__FORCE_OV0 0x80000000L 11595072188aSJason Jin #define SCLK_CNTL__R300_FORCE_VAP (1<<21) 11605072188aSJason Jin #define SCLK_CNTL__R300_FORCE_SR (1<<25) 11615072188aSJason Jin #define SCLK_CNTL__R300_FORCE_PX (1<<26) 11625072188aSJason Jin #define SCLK_CNTL__R300_FORCE_TX (1<<27) 11635072188aSJason Jin #define SCLK_CNTL__R300_FORCE_US (1<<28) 11645072188aSJason Jin #define SCLK_CNTL__R300_FORCE_SU (1<<30) 11655072188aSJason Jin #define SCLK_CNTL__FORCEON_MASK 0xffff8000L 11665072188aSJason Jin 11679c7e4b06SWolfgang Denk /* pllSCLK_CNTL2 */ 11685072188aSJason Jin #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) 11695072188aSJason Jin #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) 11705072188aSJason Jin #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) 11715072188aSJason Jin #define SCLK_CNTL2__R300_FORCE_TCL (1<<13) 11725072188aSJason Jin #define SCLK_CNTL2__R300_FORCE_CBA (1<<14) 11735072188aSJason Jin #define SCLK_CNTL2__R300_FORCE_GA (1<<15) 11745072188aSJason Jin 11759c7e4b06SWolfgang Denk /* SCLK_MORE_CNTL */ 11765072188aSJason Jin #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L 11775072188aSJason Jin #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L 11785072188aSJason Jin #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L 11795072188aSJason Jin #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L 11805072188aSJason Jin #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L 11815072188aSJason Jin #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L 11825072188aSJason Jin #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L 11835072188aSJason Jin #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L 11845072188aSJason Jin #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L 11855072188aSJason Jin #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L 11865072188aSJason Jin #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L 11875072188aSJason Jin #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L 11885072188aSJason Jin #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L 11895072188aSJason Jin #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L 11905072188aSJason Jin #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L 11915072188aSJason Jin #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L 11925072188aSJason Jin #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L 11935072188aSJason Jin #define SCLK_MORE_CNTL__FORCEON 0x00000700L 11945072188aSJason Jin 11959c7e4b06SWolfgang Denk /* MCLK_CNTL */ 11965072188aSJason Jin #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L 11975072188aSJason Jin #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L 11985072188aSJason Jin #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L 11995072188aSJason Jin #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L 12005072188aSJason Jin #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L 12015072188aSJason Jin #define MCLK_CNTL__FORCE_MCLKA 0x00010000L 12025072188aSJason Jin #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L 12035072188aSJason Jin #define MCLK_CNTL__FORCE_MCLKB 0x00020000L 12045072188aSJason Jin #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L 12055072188aSJason Jin #define MCLK_CNTL__FORCE_YCLKA 0x00040000L 12065072188aSJason Jin #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L 12075072188aSJason Jin #define MCLK_CNTL__FORCE_YCLKB 0x00080000L 12085072188aSJason Jin #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L 12095072188aSJason Jin #define MCLK_CNTL__FORCE_MC 0x00100000L 12105072188aSJason Jin #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L 12115072188aSJason Jin #define MCLK_CNTL__FORCE_AIC 0x00200000L 12125072188aSJason Jin #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L 12135072188aSJason Jin #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L 12145072188aSJason Jin #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L 12155072188aSJason Jin #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L 12165072188aSJason Jin #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) 12175072188aSJason Jin #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) 12185072188aSJason Jin 12199c7e4b06SWolfgang Denk /* MCLK_MISC */ 12205072188aSJason Jin #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L 12215072188aSJason Jin #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L 12225072188aSJason Jin #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L 12235072188aSJason Jin #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L 12245072188aSJason Jin #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L 12255072188aSJason Jin #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L 12265072188aSJason Jin #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L 12275072188aSJason Jin #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L 12285072188aSJason Jin #define MCLK_MISC__DLL_READY_LAT 0x00000100L 12295072188aSJason Jin #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L 12305072188aSJason Jin #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L 12315072188aSJason Jin #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L 12325072188aSJason Jin #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L 12335072188aSJason Jin #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L 12345072188aSJason Jin #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L 12355072188aSJason Jin #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L 12365072188aSJason Jin #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L 12375072188aSJason Jin #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L 12385072188aSJason Jin #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L 12395072188aSJason Jin #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L 12405072188aSJason Jin #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L 12415072188aSJason Jin #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L 12425072188aSJason Jin #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L 12435072188aSJason Jin #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L 12445072188aSJason Jin #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L 12455072188aSJason Jin #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L 12465072188aSJason Jin #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L 12475072188aSJason Jin #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L 12485072188aSJason Jin 12499c7e4b06SWolfgang Denk /* VCLK_ECP_CNTL */ 12505072188aSJason Jin #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L 12515072188aSJason Jin #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L 12525072188aSJason Jin #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L 12535072188aSJason Jin #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L 12545072188aSJason Jin #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L 12555072188aSJason Jin #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L 12565072188aSJason Jin #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L 12575072188aSJason Jin #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L 12585072188aSJason Jin #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) 12595072188aSJason Jin 12609c7e4b06SWolfgang Denk /* PLL_PWRMGT_CNTL */ 12615072188aSJason Jin #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L 12625072188aSJason Jin #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L 12635072188aSJason Jin #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L 12645072188aSJason Jin #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L 12655072188aSJason Jin #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L 12665072188aSJason Jin #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L 12675072188aSJason Jin #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L 12685072188aSJason Jin #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L 12695072188aSJason Jin #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L 12705072188aSJason Jin #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L 12715072188aSJason Jin #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L 12725072188aSJason Jin #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L 12735072188aSJason Jin #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L 12745072188aSJason Jin #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L 12755072188aSJason Jin #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L 12765072188aSJason Jin #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L 12775072188aSJason Jin #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L 12785072188aSJason Jin #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L 12795072188aSJason Jin #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L 12805072188aSJason Jin #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L 12815072188aSJason Jin #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L 12825072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L 12835072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L 12845072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L 12855072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L 12865072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L 12875072188aSJason Jin #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L 12885072188aSJason Jin #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L 12895072188aSJason Jin #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L 12905072188aSJason Jin #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L 12915072188aSJason Jin #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L 12925072188aSJason Jin #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L 12935072188aSJason Jin 12949c7e4b06SWolfgang Denk /* CLK_PWRMGT_CNTL */ 12955072188aSJason Jin #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L 12965072188aSJason Jin #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L 12975072188aSJason Jin #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L 12985072188aSJason Jin #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L 12995072188aSJason Jin #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L 13005072188aSJason Jin #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L 13015072188aSJason Jin #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L 13025072188aSJason Jin #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L 13035072188aSJason Jin #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L 13045072188aSJason Jin #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L 13055072188aSJason Jin #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L 13065072188aSJason Jin #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L 13075072188aSJason Jin #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L 13085072188aSJason Jin #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L 13095072188aSJason Jin #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L 13105072188aSJason Jin #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L 13115072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L 13125072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L 13135072188aSJason Jin #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L 13145072188aSJason Jin #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L 13155072188aSJason Jin #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L 13165072188aSJason Jin #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L 13175072188aSJason Jin #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L 13185072188aSJason Jin #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L 13195072188aSJason Jin #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L 13205072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L 13215072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L 13225072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L 13235072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L 13245072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L 13255072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L 13265072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L 13275072188aSJason Jin #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L 13285072188aSJason Jin #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L 13295072188aSJason Jin #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L 13305072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L 13315072188aSJason Jin #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L 13325072188aSJason Jin #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L 13335072188aSJason Jin #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L 13345072188aSJason Jin #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L 13355072188aSJason Jin #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L 13365072188aSJason Jin #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L 13375072188aSJason Jin #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L 13385072188aSJason Jin 13399c7e4b06SWolfgang Denk /* BUS_CNTL1 */ 13405072188aSJason Jin #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L 13415072188aSJason Jin #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L 13425072188aSJason Jin #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L 13435072188aSJason Jin #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L 13445072188aSJason Jin #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L 13455072188aSJason Jin #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L 13465072188aSJason Jin #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L 13475072188aSJason Jin #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L 13485072188aSJason Jin #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L 13495072188aSJason Jin #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L 13505072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L 13515072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L 13525072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L 13535072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L 13545072188aSJason Jin #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L 13555072188aSJason Jin #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L 13565072188aSJason Jin #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L 13575072188aSJason Jin #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L 13585072188aSJason Jin #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L 13595072188aSJason Jin #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L 13605072188aSJason Jin #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L 13615072188aSJason Jin #define BUS_CNTL1__AGPCLK_VALID 0x80000000L 13625072188aSJason Jin 13639c7e4b06SWolfgang Denk /* BUS_CNTL1 */ 13645072188aSJason Jin #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 13655072188aSJason Jin #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 13665072188aSJason Jin #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 13675072188aSJason Jin #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 13685072188aSJason Jin #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 13695072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 13705072188aSJason Jin #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 13715072188aSJason Jin #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a 13725072188aSJason Jin #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b 13735072188aSJason Jin #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a 13745072188aSJason Jin #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c 13755072188aSJason Jin #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f 13765072188aSJason Jin 13779c7e4b06SWolfgang Denk /* CRTC_OFFSET_CNTL */ 13785072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL 13795072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L 13805072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L 13815072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L 13825072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L 13835072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L 13845072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L 13855072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L 13865072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L 13875072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L 13885072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L 13895072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L 13905072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L 13915072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L 13925072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L 13935072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L 13945072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L 13955072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L 13965072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L 13975072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L 13985072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L 13995072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L 14005072188aSJason Jin #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L 14015072188aSJason Jin 14029c7e4b06SWolfgang Denk /* CRTC_GEN_CNTL */ 14035072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L 14045072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L 14055072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L 14065072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L 14075072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L 14085072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L 14095072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L 14105072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L 14115072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L 14125072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L 14135072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L 14145072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L 14155072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L 14165072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L 14175072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L 14185072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L 14195072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L 14205072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L 14215072188aSJason Jin #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L 14225072188aSJason Jin 14239c7e4b06SWolfgang Denk /* CRTC2_GEN_CNTL */ 14245072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L 14255072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L 14265072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L 14275072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L 14285072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L 14295072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L 14305072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L 14315072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L 14325072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L 14335072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L 14345072188aSJason Jin #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L 14355072188aSJason Jin #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L 14365072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L 14375072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L 14385072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L 14395072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L 14405072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L 14415072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L 14425072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L 14435072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L 14445072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L 14455072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L 14465072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L 14475072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L 14485072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L 14495072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L 14505072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L 14515072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L 14525072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L 14535072188aSJason Jin #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L 14545072188aSJason Jin 14559c7e4b06SWolfgang Denk /* AGP_CNTL */ 14565072188aSJason Jin #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL 14575072188aSJason Jin #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L 14585072188aSJason Jin #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L 14595072188aSJason Jin #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L 14605072188aSJason Jin #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L 14615072188aSJason Jin #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L 14625072188aSJason Jin #define AGP_CNTL__EN_2X_STBB 0x00000400L 14635072188aSJason Jin #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L 14645072188aSJason Jin #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L 14655072188aSJason Jin #define AGP_CNTL__SBA_DIS_MASK 0x00001000L 14665072188aSJason Jin #define AGP_CNTL__SBA_DIS 0x00001000L 14675072188aSJason Jin #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L 14685072188aSJason Jin #define AGP_CNTL__AGP_REV_ID 0x00002000L 14695072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L 14705072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L 14715072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L 14725072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L 14735072188aSJason Jin #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L 14745072188aSJason Jin #define AGP_CNTL__FORCE_INT_VREF 0x00010000L 14755072188aSJason Jin #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L 14765072188aSJason Jin #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L 14775072188aSJason Jin #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L 14785072188aSJason Jin #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L 14795072188aSJason Jin #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L 14805072188aSJason Jin #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L 14815072188aSJason Jin #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L 14825072188aSJason Jin #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L 14835072188aSJason Jin #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L 14845072188aSJason Jin #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L 14855072188aSJason Jin #define AGP_CNTL__EN_RBFCALM 0x00800000L 14865072188aSJason Jin #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L 14875072188aSJason Jin #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L 14885072188aSJason Jin #define AGP_CNTL__DIS_RBF_MASK 0x02000000L 14895072188aSJason Jin #define AGP_CNTL__DIS_RBF 0x02000000L 14905072188aSJason Jin #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L 14915072188aSJason Jin #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L 14925072188aSJason Jin #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L 14935072188aSJason Jin #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L 14945072188aSJason Jin 14959c7e4b06SWolfgang Denk /* AGP_CNTL */ 14965072188aSJason Jin #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 14975072188aSJason Jin #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 14985072188aSJason Jin #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 14995072188aSJason Jin #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a 15005072188aSJason Jin #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b 15015072188aSJason Jin #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c 15025072188aSJason Jin #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d 15035072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e 15045072188aSJason Jin #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f 15055072188aSJason Jin #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 15065072188aSJason Jin #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 15075072188aSJason Jin #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 15085072188aSJason Jin #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 15095072188aSJason Jin #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 15105072188aSJason Jin #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 15115072188aSJason Jin #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 15125072188aSJason Jin #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 15135072188aSJason Jin #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 15145072188aSJason Jin #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a 15155072188aSJason Jin #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b 15165072188aSJason Jin #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e 15175072188aSJason Jin 15189c7e4b06SWolfgang Denk /* DISP_MISC_CNTL */ 15195072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L 15205072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L 15215072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L 15225072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L 15235072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L 15245072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L 15255072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L 15265072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L 15275072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L 15285072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L 15295072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L 15305072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L 15315072188aSJason Jin #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L 15325072188aSJason Jin #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L 15335072188aSJason Jin #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L 15345072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L 15355072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L 15365072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L 15375072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L 15385072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L 15395072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L 15405072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L 15415072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L 15425072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L 15435072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L 15445072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L 15455072188aSJason Jin #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L 15465072188aSJason Jin #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L 15475072188aSJason Jin #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L 15485072188aSJason Jin #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L 15495072188aSJason Jin 15509c7e4b06SWolfgang Denk /* DISP_PWR_MAN */ 15515072188aSJason Jin #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L 15525072188aSJason Jin #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L 15535072188aSJason Jin #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L 15545072188aSJason Jin #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L 15555072188aSJason Jin #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L 15565072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L 15575072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L 15585072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L 15595072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L 15605072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L 15615072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L 15625072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L 15635072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L 15645072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L 15655072188aSJason Jin #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L 15665072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L 15675072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L 15685072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L 15695072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L 15705072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L 15715072188aSJason Jin #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L 15725072188aSJason Jin #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L 15735072188aSJason Jin #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L 15745072188aSJason Jin #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L 15755072188aSJason Jin #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L 15765072188aSJason Jin #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L 15775072188aSJason Jin #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L 15785072188aSJason Jin 15799c7e4b06SWolfgang Denk /* MC_IND_INDEX */ 15805072188aSJason Jin #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL 15815072188aSJason Jin #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L 15825072188aSJason Jin #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L 15835072188aSJason Jin 15849c7e4b06SWolfgang Denk /* MC_IND_DATA */ 15855072188aSJason Jin #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL 15865072188aSJason Jin 15879c7e4b06SWolfgang Denk /* MC_CHP_IO_CNTL_A1 */ 15885072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 15895072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 15905072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 15915072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 15925072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 15935072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 15945072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 15955072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 15965072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 15975072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 15985072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a 15995072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c 16005072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e 16015072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 16025072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 16035072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 16045072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 16055072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 16065072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 16075072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a 16085072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c 16095072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e 16105072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f 16115072188aSJason Jin 16129c7e4b06SWolfgang Denk /* MC_CHP_IO_CNTL_B1 */ 16135072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 16145072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 16155072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 16165072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 16175072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 16185072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 16195072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 16205072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 16215072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 16225072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 16235072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a 16245072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c 16255072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e 16265072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 16275072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 16285072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 16295072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 16305072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 16315072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 16325072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a 16335072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c 16345072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e 16355072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f 16365072188aSJason Jin 16379c7e4b06SWolfgang Denk /* MC_CHP_IO_CNTL_A1 */ 16385072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L 16395072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L 16405072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L 16415072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L 16425072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L 16435072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L 16445072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L 16455072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L 16465072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L 16475072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L 16485072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L 16495072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L 16505072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L 16515072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L 16525072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L 16535072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L 16545072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L 16555072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L 16565072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L 16575072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L 16585072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L 16595072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L 16605072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L 16615072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L 16625072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L 16635072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L 16645072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L 16655072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L 16665072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L 16675072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L 16685072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L 16695072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L 16705072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L 16715072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L 16725072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L 16735072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L 16745072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L 16755072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L 16765072188aSJason Jin #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L 16775072188aSJason Jin 16789c7e4b06SWolfgang Denk /* MC_CHP_IO_CNTL_B1 */ 16795072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L 16805072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L 16815072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L 16825072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L 16835072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L 16845072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L 16855072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L 16865072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L 16875072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L 16885072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L 16895072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L 16905072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L 16915072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L 16925072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L 16935072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L 16945072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L 16955072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L 16965072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L 16975072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L 16985072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L 16995072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L 17005072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L 17015072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L 17025072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L 17035072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L 17045072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L 17055072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L 17065072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L 17075072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L 17085072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L 17095072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L 17105072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L 17115072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L 17125072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L 17135072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L 17145072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L 17155072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L 17165072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L 17175072188aSJason Jin #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L 17185072188aSJason Jin 17199c7e4b06SWolfgang Denk /* MEM_SDRAM_MODE_REG */ 17205072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL 17215072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L 17225072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L 17235072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L 17245072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L 17255072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L 17265072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L 17275072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L 17285072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L 17295072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L 17305072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L 17315072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L 17325072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L 17335072188aSJason Jin #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L 17345072188aSJason Jin #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L 17355072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L 17365072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L 17375072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L 17385072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L 17395072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L 17405072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L 17415072188aSJason Jin 17429c7e4b06SWolfgang Denk /* MEM_SDRAM_MODE_REG */ 17435072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 17445072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 17455072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 17465072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 17475072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 17485072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 17495072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a 17505072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b 17515072188aSJason Jin #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c 17525072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d 17535072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e 17545072188aSJason Jin #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f 17555072188aSJason Jin 17569c7e4b06SWolfgang Denk /* MEM_REFRESH_CNTL */ 17575072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL 17585072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L 17595072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L 17605072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L 17615072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L 17625072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L 17635072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L 17645072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L 17655072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L 17665072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L 17675072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L 17685072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L 17695072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L 17705072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L 17715072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L 17725072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L 17735072188aSJason Jin #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L 17745072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L 17755072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L 17765072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L 17775072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L 17785072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L 17795072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L 17805072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L 17815072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L 17825072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L 17835072188aSJason Jin #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L 17845072188aSJason Jin #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L 17855072188aSJason Jin 17869c7e4b06SWolfgang Denk /* MC_STATUS */ 17875072188aSJason Jin #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L 17885072188aSJason Jin #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L 17895072188aSJason Jin #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L 17905072188aSJason Jin #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L 17915072188aSJason Jin #define MC_STATUS__MC_IDLE_MASK 0x00000004L 17925072188aSJason Jin #define MC_STATUS__MC_IDLE 0x00000004L 17935072188aSJason Jin #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L 17945072188aSJason Jin #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L 17955072188aSJason Jin #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L 17965072188aSJason Jin #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L 17975072188aSJason Jin #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L 17985072188aSJason Jin #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L 17995072188aSJason Jin #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L 18005072188aSJason Jin #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L 18015072188aSJason Jin #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L 18025072188aSJason Jin #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L 18035072188aSJason Jin 18049c7e4b06SWolfgang Denk /* MDLL_CKO */ 18055072188aSJason Jin #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L 18065072188aSJason Jin #define MDLL_CKO__MCKOA_SLEEP 0x00000001L 18075072188aSJason Jin #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L 18085072188aSJason Jin #define MDLL_CKO__MCKOA_RESET 0x00000002L 18095072188aSJason Jin #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL 18105072188aSJason Jin #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L 18115072188aSJason Jin #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L 18125072188aSJason Jin #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L 18135072188aSJason Jin #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L 18145072188aSJason Jin #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L 18155072188aSJason Jin #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L 18165072188aSJason Jin #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L 18175072188aSJason Jin #define MDLL_CKO__MCKOB_SLEEP 0x00010000L 18185072188aSJason Jin #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L 18195072188aSJason Jin #define MDLL_CKO__MCKOB_RESET 0x00020000L 18205072188aSJason Jin #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L 18215072188aSJason Jin #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L 18225072188aSJason Jin #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L 18235072188aSJason Jin #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L 18245072188aSJason Jin #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L 18255072188aSJason Jin #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L 18265072188aSJason Jin #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L 18275072188aSJason Jin 18289c7e4b06SWolfgang Denk /* MDLL_RDCKA */ 18295072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L 18305072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L 18315072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L 18325072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L 18335072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL 18345072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L 18355072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L 18365072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L 18375072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L 18385072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L 18395072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L 18405072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L 18415072188aSJason Jin #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L 18425072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L 18435072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L 18445072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L 18455072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L 18465072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L 18475072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L 18485072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L 18495072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L 18505072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L 18515072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L 18525072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L 18535072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L 18545072188aSJason Jin #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L 18555072188aSJason Jin 18569c7e4b06SWolfgang Denk /* MDLL_RDCKB */ 18575072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L 18585072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L 18595072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L 18605072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L 18615072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL 18625072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L 18635072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L 18645072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L 18655072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L 18665072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L 18675072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L 18685072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L 18695072188aSJason Jin #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L 18705072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L 18715072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L 18725072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L 18735072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L 18745072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L 18755072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L 18765072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L 18775072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L 18785072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L 18795072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L 18805072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L 18815072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L 18825072188aSJason Jin #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L 18835072188aSJason Jin 18845072188aSJason Jin #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L 18855072188aSJason Jin #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L 18865072188aSJason Jin #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L 18875072188aSJason Jin #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L 18885072188aSJason Jin #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L 18895072188aSJason Jin #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L 18905072188aSJason Jin #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L 18915072188aSJason Jin #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L 18925072188aSJason Jin 18935072188aSJason Jin #define pllCLK_PIN_CNTL 0x0001 18945072188aSJason Jin #define pllPPLL_CNTL 0x0002 18955072188aSJason Jin #define pllPPLL_REF_DIV 0x0003 18965072188aSJason Jin #define pllPPLL_DIV_0 0x0004 18975072188aSJason Jin #define pllPPLL_DIV_1 0x0005 18985072188aSJason Jin #define pllPPLL_DIV_2 0x0006 18995072188aSJason Jin #define pllPPLL_DIV_3 0x0007 19005072188aSJason Jin #define pllVCLK_ECP_CNTL 0x0008 19015072188aSJason Jin #define pllHTOTAL_CNTL 0x0009 19025072188aSJason Jin #define pllM_SPLL_REF_FB_DIV 0x000A 19035072188aSJason Jin #define pllAGP_PLL_CNTL 0x000B 19045072188aSJason Jin #define pllSPLL_CNTL 0x000C 19055072188aSJason Jin #define pllSCLK_CNTL 0x000D 19065072188aSJason Jin #define pllMPLL_CNTL 0x000E 19075072188aSJason Jin #define pllMDLL_CKO 0x000F 19085072188aSJason Jin #define pllMDLL_RDCKA 0x0010 19095072188aSJason Jin #define pllMDLL_RDCKB 0x0011 19105072188aSJason Jin #define pllMCLK_CNTL 0x0012 19115072188aSJason Jin #define pllPLL_TEST_CNTL 0x0013 19125072188aSJason Jin #define pllCLK_PWRMGT_CNTL 0x0014 19135072188aSJason Jin #define pllPLL_PWRMGT_CNTL 0x0015 19145072188aSJason Jin #define pllCG_TEST_MACRO_RW_WRITE 0x0016 19155072188aSJason Jin #define pllCG_TEST_MACRO_RW_READ 0x0017 19165072188aSJason Jin #define pllCG_TEST_MACRO_RW_DATA 0x0018 19175072188aSJason Jin #define pllCG_TEST_MACRO_RW_CNTL 0x0019 19185072188aSJason Jin #define pllDISP_TEST_MACRO_RW_WRITE 0x001A 19195072188aSJason Jin #define pllDISP_TEST_MACRO_RW_READ 0x001B 19205072188aSJason Jin #define pllDISP_TEST_MACRO_RW_DATA 0x001C 19215072188aSJason Jin #define pllDISP_TEST_MACRO_RW_CNTL 0x001D 19225072188aSJason Jin #define pllSCLK_CNTL2 0x001E 19235072188aSJason Jin #define pllMCLK_MISC 0x001F 19245072188aSJason Jin #define pllTV_PLL_FINE_CNTL 0x0020 19255072188aSJason Jin #define pllTV_PLL_CNTL 0x0021 19265072188aSJason Jin #define pllTV_PLL_CNTL1 0x0022 19275072188aSJason Jin #define pllTV_DTO_INCREMENTS 0x0023 19285072188aSJason Jin #define pllSPLL_AUX_CNTL 0x0024 19295072188aSJason Jin #define pllMPLL_AUX_CNTL 0x0025 19305072188aSJason Jin #define pllP2PLL_CNTL 0x002A 19315072188aSJason Jin #define pllP2PLL_REF_DIV 0x002B 19325072188aSJason Jin #define pllP2PLL_DIV_0 0x002C 19335072188aSJason Jin #define pllPIXCLKS_CNTL 0x002D 19345072188aSJason Jin #define pllHTOTAL2_CNTL 0x002E 19355072188aSJason Jin #define pllSSPLL_CNTL 0x0030 19365072188aSJason Jin #define pllSSPLL_REF_DIV 0x0031 19375072188aSJason Jin #define pllSSPLL_DIV_0 0x0032 19385072188aSJason Jin #define pllSS_INT_CNTL 0x0033 19395072188aSJason Jin #define pllSS_TST_CNTL 0x0034 19405072188aSJason Jin #define pllSCLK_MORE_CNTL 0x0035 19415072188aSJason Jin 19425072188aSJason Jin #define ixMC_PERF_CNTL 0x0000 19435072188aSJason Jin #define ixMC_PERF_SEL 0x0001 19445072188aSJason Jin #define ixMC_PERF_REGION_0 0x0002 19455072188aSJason Jin #define ixMC_PERF_REGION_1 0x0003 19465072188aSJason Jin #define ixMC_PERF_COUNT_0 0x0004 19475072188aSJason Jin #define ixMC_PERF_COUNT_1 0x0005 19485072188aSJason Jin #define ixMC_PERF_COUNT_2 0x0006 19495072188aSJason Jin #define ixMC_PERF_COUNT_3 0x0007 19505072188aSJason Jin #define ixMC_PERF_COUNT_MEMCH_A 0x0008 19515072188aSJason Jin #define ixMC_PERF_COUNT_MEMCH_B 0x0009 19525072188aSJason Jin #define ixMC_IMP_CNTL 0x000A 19535072188aSJason Jin #define ixMC_CHP_IO_CNTL_A0 0x000B 19545072188aSJason Jin #define ixMC_CHP_IO_CNTL_A1 0x000C 19555072188aSJason Jin #define ixMC_CHP_IO_CNTL_B0 0x000D 19565072188aSJason Jin #define ixMC_CHP_IO_CNTL_B1 0x000E 19575072188aSJason Jin #define ixMC_IMP_CNTL_0 0x000F 19585072188aSJason Jin #define ixTC_MISMATCH_1 0x0010 19595072188aSJason Jin #define ixTC_MISMATCH_2 0x0011 19605072188aSJason Jin #define ixMC_BIST_CTRL 0x0012 19615072188aSJason Jin #define ixREG_COLLAR_WRITE 0x0013 19625072188aSJason Jin #define ixREG_COLLAR_READ 0x0014 19635072188aSJason Jin #define ixR300_MC_IMP_CNTL 0x0018 19645072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_A0 0x0019 19655072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_A1 0x001a 19665072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_B0 0x001b 19675072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_B1 0x001c 19685072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_C0 0x001d 19695072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_C1 0x001e 19705072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_D0 0x001f 19715072188aSJason Jin #define ixR300_MC_CHP_IO_CNTL_D1 0x0020 19725072188aSJason Jin #define ixR300_MC_IMP_CNTL_0 0x0021 19735072188aSJason Jin #define ixR300_MC_ELPIDA_CNTL 0x0022 19745072188aSJason Jin #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 19755072188aSJason Jin #define ixR300_MC_READ_CNTL_CD 0x0024 19765072188aSJason Jin #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 19775072188aSJason Jin #define ixR300_MC_DEBUG_CNTL 0x0026 19785072188aSJason Jin #define ixR300_MC_BIST_CNTL_0 0x0028 19795072188aSJason Jin #define ixR300_MC_BIST_CNTL_1 0x0029 19805072188aSJason Jin #define ixR300_MC_BIST_CNTL_2 0x002a 19815072188aSJason Jin #define ixR300_MC_BIST_CNTL_3 0x002b 19825072188aSJason Jin #define ixR300_MC_BIST_CNTL_4 0x002c 19835072188aSJason Jin #define ixR300_MC_BIST_CNTL_5 0x002d 19845072188aSJason Jin #define ixR300_MC_IMP_STATUS 0x002e 19855072188aSJason Jin #define ixR300_MC_DLL_CNTL 0x002f 19865072188aSJason Jin #define NB_TOM 0x15C 19875072188aSJason Jin 19885072188aSJason Jin #endif /* _RADEON_H */ 1989