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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-am654.yaml109 ti,otap-del-sel-ddr52:
110 description: Output tap delay for eMMC DDR52 timing
167 ti,itap-del-sel-ddr52:
168 description: Input tap delay for MMC DDR52 timing
234 ti,otap-del-sel-ddr52 = <0x5>;
239 ti,itap-del-sel-ddr52 = <0x3>;
H A Dsdhci-sprd.txt38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
H A Dmmc-controller.yaml348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-k3.c85 {0}, /* 8: DDR52 */
97 {0}, /* 8: DDR52 */
H A Dsdhci-acpi.c499 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
500 * happens while in DDR52 and HS modes. This has not been observed to in amd_select_drive_strength()
532 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
H A Dsdhci_am654.c131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
H A Ddw_mmc-rockchip.c46 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
H A Dsdhci-sprd.c111 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
H A Dsunxi-mmc.c783 * We currently only support the standard MMC DDR52 mode. in sunxi_mmc_clk_set_rate()
H A Dsdhci-of-arasan.c1322 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi150 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
/openbmc/linux/drivers/mmc/core/
H A Ddebugfs.c145 str = "mmc DDR52"; in mmc_ios_show()
H A Dhost.c257 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-ddr52", in mmc_of_parse_clk_phase()
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-main.dtsi613 ti,otap-del-sel-ddr52 = <0x6>;
617 ti,itap-del-sel-ddr52 = <0x3>;
H A Dk3-am65-main.dtsi447 ti,otap-del-sel-ddr52 = <0x5>;
469 ti,otap-del-sel-ddr52 = <0x4>;
H A Dk3-am62-main.dtsi541 ti,otap-del-sel-ddr52 = <0x5>;
H A Dk3-j721e-main.dtsi1482 ti,otap-del-sel-ddr52 = <0x5>;
1487 ti,itap-del-sel-ddr52 = <0x3>;
H A Dk3-j7200-main.dtsi663 ti,otap-del-sel-ddr52 = <0x6>;
H A Dk3-j784s4-main.dtsi627 ti,otap-del-sel-ddr52 = <0x6>;
H A Dk3-j721s2-main.dtsi732 ti,otap-del-sel-ddr52 = <0x6>;
/openbmc/u-boot/drivers/mmc/
H A Dmmc.c148 [MMC_DDR_52] = "MMC DDR52 (52MHz)", in mmc_mode_name()