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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Dfsl-imx-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale(NXP) IMX8/9 DDR performance monitor
10 - Frank Li <frank.li@nxp.com>
15 - enum:
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
[all …]
H A Damlogic,g12-ddr-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic G12 DDR performance monitor
10 - Jiucheng Xu <jiucheng.xu@amlogic.com>
13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
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H A Dmarvell-cn10k-ddr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell CN10K DDR performance monitor
10 - Bharat Bhushan <bbhushan2@marvell.com>
15 - enum:
16 - marvell,cn10k-ddr-pmu
22 - compatible
23 - reg
[all …]
/openbmc/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
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H A Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
50 /* DDR Perf hardware feature */
55 unsigned int quirks; /* quirks needed for different DDR Perf core */
56 const char *identifier; /* system PMU identifier for userspace */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
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H A Dmarvell_cn10k_ddr_pmu.c1 // SPDX-License-Identifier: GPL-2.0
48 /* Two dedicated event counters for DDR reads and writes */
54 * DO NOT change these event-id numbers, they are used to
125 struct pmu pmu; member
135 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
144 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in cn10k_ddr_pmu_event_show()
217 PMU_FORMAT_ATTR(event, "config:0-8");
233 struct cn10k_ddr_pmu *pmu = dev_get_drvdata(dev); in cn10k_ddr_perf_cpumask_show() local
235 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in cn10k_ddr_perf_cpumask_show()
274 *event_bitmap = (1ULL << (eventid - 1)); in ddr_perf_get_event_bitmap()
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H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
32 * 32bit counters monitor counter-specific events in addition to counting reference events
45 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
53 const char *identifier; /* system PMU identifier for userspace */
57 struct pmu pmu; member
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
84 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
104 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
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H A Dalibaba_uncore_drw_pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Alibaba DDR Sub-System Driveway PMU driver
55 /* PMU EVENT SEL 0-3 are paired in 32-bit registers on a 4-byte stride */
57 /* counter 0-3 use sel0, counter 4-7 use sel1...*/
65 /* PMU COMMON COUNTER 0-15, are paired in 32-bit registers on a 4-byte stride */
105 struct pmu pmu; member
108 #define to_ali_drw_pmu(p) (container_of(p, struct ali_drw_pmu, pmu))
111 #define GET_DRW_EVENTID(event) FIELD_GET(DRW_CONFIG_EVENTID, (event)->attr.config)
120 return sprintf(buf, "%s\n", (char *)eattr->var); in ali_drw_pmu_format_show()
124 * PMU event attributes
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/openbmc/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
18 The Driveway PMU devices are named as ali_drw_<sys_base_addr> with perf.
19 For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
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H A Dindex.rst1 .. SPDX-License-Identifier: GPL-2.0
10 hisi-pmu
11 hisi-pcie-pmu
12 hns3-pmu
13 imx-ddr
16 arm-ccn
17 arm-cmn
18 xgene-pmu
20 thunderx2-pmu
22 nvidia-pmu
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H A Dhisi-pmu.rst2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
15 HiSilicon SoC uncore PMU driver
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
39 ID used to count the uncore PMU event.
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H A Dimx-ddr.rst2 Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
39 --AXI_MASKING defines which bits of AxID are meaningful for the matching.
[all …]
H A Dmeson-ddr-pmu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
10 to show if the performance bottleneck is on DDR bandwidth.
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
24 Below are DDR access request event filter keywords:
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2020 NXP
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
H A Dimx8dxl-ss-ddr.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 compatible = "fsl,imx8-ddr-pmu";
/openbmc/linux/drivers/perf/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "HiSilicon SoC PMU drivers"
7 Agent performance monitor and DDR Controller performance monitor.
10 tristate "HiSilicon PCIE PERF PMU"
13 Provide support for HiSilicon PCIe performance monitoring unit (PMU)
15 Adds the PCIe PMU into perf events system for monitoring latency,
19 tristate "HNS3 PERF PMU"
23 Provide support for HNS3 performance monitoring unit (PMU) RCiEP
25 Adds the HNS3 PMU into perf events system for monitoring latency,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
20 Node to get DDR loading. Refer to
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
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/openbmc/linux/drivers/perf/amlogic/
H A Dmeson_g12_ddr_pmu.c1 // SPDX-License-Identifier: GPL-2.0
43 PMU_FORMAT_ATTR(event, "config:0-7");
127 /* calculate ddr clock */
135 val = readl(info->pll_reg); in dmc_g12_get_freq_quick()
179 r = readl(db->ddr_reg[0] + (DMC_MON_G12_CTRL0 + (i << 2))); in g12_dump_reg()
182 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT); in g12_dump_reg()
184 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT); in g12_dump_reg()
186 r = readl(db->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT); in g12_dump_reg()
188 r = readl(db->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT); in g12_dump_reg()
190 r = readl(db->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT); in g12_dump_reg()
[all …]
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_train.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/ddr.h>
20 dram_cfg = dram_timing->ddrphy_cfg; in ddr_cfg_phy()
21 num = dram_timing->ddrphy_cfg_num; in ddr_cfg_phy()
24 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); in ddr_cfg_phy()
29 fsp_msg = dram_timing->fsp_msg; in ddr_cfg_phy()
30 for (i = 0; i < dram_timing->fsp_msg_num; i++) { in ddr_cfg_phy()
31 debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); in ddr_cfg_phy()
33 ddrphy_init_set_dfi_clk(fsp_msg->drate); in ddr_cfg_phy()
37 ddr_load_train_firmware(fsp_msg->fw_type); in ddr_cfg_phy()
[all …]
H A Dddrphy_utils.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/ddr.h>
11 #include <asm/arch/ddr.h>
68 debug("[PMU Major message = 0x%08x]\n", mail); in decode_major_message()
77 debug("PMU String index = 0x%08x\n", string_index); in decode_streaming_message()
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A DKconfig58 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
61 string "PMU firmware"
72 bool "Disable DDR MMU mapping"
74 This option configures MMU with no DDR to avoid speculative
75 access to DDR memory where DDR is not present.
90 Include psu_init to full u-boot. SPL include psu_init by default.
/openbmc/u-boot/doc/
H A DREADME.440-DDR-performance1 AMCC suggested to set the PMU bit to 0 for best performace on the
2 PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
11 ----------------------------------------
12 SDRAM0_CFG0[PMU] = 1 (U-Boot default for Bamboo, Yosemite and Yellowstone)
13 ----------------------------------------
15 -------------------------------------------------------------
17 -------------------------------------------------------------
22 -------------------------------------------------------------
28 -------------------------------------------------------------
29 WARNING -- The above is only a rough guideline.
[all …]
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a15";
[all …]
/openbmc/linux/tools/perf/tests/
H A Dpmu-events.c1 // SPDX-License-Identifier: GPL-2.0
3 #include "parse-events.h"
4 #include "pmu.h"
12 #include "../pmu-events/pmu-events.h"
17 #include "util/parse-events.h"
22 /* used for matching against events from generated pmu-events.c */
36 /* PMU which we should match against */
41 struct perf_pmu pmu; member
47 .pmu = "default_core",
59 .pmu = "default_core",
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