Lines Matching +full:ddr +full:- +full:pmu

1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/ddr.h>
20 	dram_cfg = dram_timing->ddrphy_cfg;  in ddr_cfg_phy()
21 	num  = dram_timing->ddrphy_cfg_num;  in ddr_cfg_phy()
24 		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);  in ddr_cfg_phy()
29 	fsp_msg = dram_timing->fsp_msg;  in ddr_cfg_phy()
30 	for (i = 0; i < dram_timing->fsp_msg_num; i++) {  in ddr_cfg_phy()
31 		debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);  in ddr_cfg_phy()
33 		ddrphy_init_set_dfi_clk(fsp_msg->drate);  in ddr_cfg_phy()
37 		ddr_load_train_firmware(fsp_msg->fw_type);  in ddr_cfg_phy()
40 		dram_cfg = fsp_msg->fsp_cfg;  in ddr_cfg_phy()
41 		num = fsp_msg->fsp_cfg_num;  in ddr_cfg_phy()
43 			dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);  in ddr_cfg_phy()
48 		 * -------------------- excute the firmware --------------------  in ddr_cfg_phy()
50 		 * PMU out of reset and stall, then the firwmare will be run  in ddr_cfg_phy()
51 		 * 1. reset the PMU;  in ddr_cfg_phy()
55 		 * -------------------------------------------------------------  in ddr_cfg_phy()
70 		ddrphy_init_read_msg_block(fsp_msg->fw_type);  in ddr_cfg_phy()
77 	dram_cfg = dram_timing->ddrphy_pie;  in ddr_cfg_phy()
78 	num = dram_timing->ddrphy_pie_num;  in ddr_cfg_phy()
80 		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);  in ddr_cfg_phy()
84 	/* save the ddr PHY trained CSR in memory for low power use */  in ddr_cfg_phy()