History log of /openbmc/u-boot/doc/README.440-DDR-performance (Results 1 – 5 of 5)
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# 57dc53a7 08-Feb-2016 Tom Rini <trini@konsulko.com>

Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
# a187559e 05-Feb-2016 Bin Meng <bmeng.cn@gmail.com>

Use correct spelling of "U-Boot"

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed

Use correct spelling of "U-Boot"

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>

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# 281f69ed 09-Aug-2006 Jon Loeliger <jdl@freescale.com>

Merge branch 'wd'
# 98280e3d 07-Aug-2006 Wolfgang Denk <wd@pollux.denx.de>

Merge with /home/wd/git/u-boot/master
# a2c95a72 28-Jul-2006 Stefan Roese <sr@denx.de>

PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for de

PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006

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