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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmicrochip,mcp3911.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Marcus Folkesson <marcus.folkesson@gmail.com>
12 - Kent Gustavsson <nedo80@gmail.com>
21 - microchip,mcp3911
26 spi-max-frequency:
39 microchip,data-ready-hiz:
41 Data Ready Pin Inactive State Control
42 true = The DR pin state is high-impedance
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/openbmc/linux/tools/spi/
H A Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
175 printf("Usage: %s [-2348CDFHILMNORSZbdilopsv]\n", prog); in print_usage()
177 " -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
178 " -s --speed max speed (Hz)\n" in print_usage()
179 " -d --delay delay (usec)\n" in print_usage()
180 " -l --loop loopback\n" in print_usage()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
53 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
64 /* 40M1G25 mode init data */
67 /*-----------------------------------------------------------*/
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
263 static void reg_set_indirect(u32 reg, u16 data, u16 mask) in reg_set_indirect() argument
266 reg_set(rh_vsreg_data, data, mask); in reg_set_indirect()
286 * 1. Select 40-bit data width width in comphy_sata_power_up()
312 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
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/openbmc/linux/drivers/iio/adc/
H A Dmcp3911.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
91 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
92 ret = spi_write_then_read(adc->spi, &reg, 1, val, len); in mcp3911_read()
97 *val >>= ((4 - len) * 8); in mcp3911_read()
98 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, in mcp3911_read()
105 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); in mcp3911_write()
107 val <<= (3 - len) * 8; in mcp3911_write()
109 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); in mcp3911_write()
111 return spi_write(adc->spi, &val, len + 1); in mcp3911_write()
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/openbmc/linux/drivers/media/i2c/
H A Dmax2175.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
30 #define mxm_dbg(ctx, fmt, arg...) dev_dbg(&ctx->client->dev, fmt, ## arg)
31 #define mxm_err(ctx, fmt, arg...) dev_err(&ctx->client->dev, fmt, ## arg)
264 struct v4l2_subdev sd; /* Sub-device */
273 struct v4l2_ctrl *hsls; /* High-side/Low-side polarity */
288 bool am_hiz; /* AM Hi-Z filter */
321 ret = regmap_read(ctx->regmap, idx, &regval); in max2175_read()
334 ret = regmap_write(ctx->regmap, idx, val); in max2175_write()
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/openbmc/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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