1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2015-2016 Marvell International Ltd.
53 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
64 /* 40M1G25 mode init data */
67 	/*-----------------------------------------------------------*/
144 	for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {  in comphy_poll_reg()
263 static void reg_set_indirect(u32 reg, u16 data, u16 mask)  in reg_set_indirect()  argument
266 	reg_set(rh_vsreg_data, data, mask);  in reg_set_indirect()
286 	 * 1. Select 40-bit data width width  in comphy_sata_power_up()
312 	 * 5. Set vendor-specific configuration (??)  in comphy_sata_power_up()
339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)  in usb3_reg_set16()  argument
343 	 * through indirect Address and Data registers INDIR_ACC_PHY_ADDR  in usb3_reg_set16()
350 		reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,  in usb3_reg_set16()
353 		reg_set16(phy_addr(USB3, reg), data, mask);  in usb3_reg_set16()
380 	/* set PRD_TXDEEMPH (3.5db de-emph) */  in comphy_usb3_power_up()
385 	 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency  in comphy_usb3_power_up()
386 	 * Set BIT6: Tx detect Rx at HiZ mode  in comphy_usb3_power_up()
387 	 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db  in comphy_usb3_power_up()
406 	/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */  in comphy_usb3_power_up()
445 	 * 7. Set 20-bit data width  in comphy_usb3_power_up()
598 	/* Assert PLL is ready */  in comphy_usb2_power_up()
784 	 * 13. Program COMPHY register SEL_BITS to set correct parallel data  in comphy_sgmii_power_up()
805 	 *     group to get the related GEN table during real chip bring-up.  in comphy_sgmii_power_up()
811 	debug("Running C-DPI phy init %s mode\n",  in comphy_sgmii_power_up()
863 	 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.  in comphy_sgmii_power_up()
892 	const void *blob = gd->fdt_blob;  in comphy_dedicated_phys_init()
903 				blob, -1, "marvell,armada3700-ehci");  in comphy_dedicated_phys_init()
906 				blob, -1, "marvell,armada3700-xhci");  in comphy_dedicated_phys_init()
925 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
926 					     "marvell,armada-3700-ahci");  in comphy_dedicated_phys_init()
941 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
942 					     "marvell,armada-8k-sdhci");  in comphy_dedicated_phys_init()
945 			blob, -1, "marvell,armada-3700-sdhci");  in comphy_dedicated_phys_init()
969 	u32 comphy_max_count = chip_cfg->comphy_lanes_count;  in comphy_a3700_init()
975 	chip_cfg->mux_data = a3700_comphy_mux_data;  in comphy_a3700_init()
982 		      comphy_map->type, comphy_map->invert);  in comphy_a3700_init()
984 		switch (comphy_map->type) {  in comphy_a3700_init()
990 			ret = comphy_pcie_power_up(comphy_map->speed,  in comphy_a3700_init()
991 						   comphy_map->invert);  in comphy_a3700_init()
997 						   comphy_map->type,  in comphy_a3700_init()
998 						   comphy_map->speed,  in comphy_a3700_init()
999 						   comphy_map->invert);  in comphy_a3700_init()
1004 			ret = comphy_sgmii_power_up(lane, comphy_map->speed,  in comphy_a3700_init()
1005 						    comphy_map->invert);  in comphy_a3700_init()
1015 			printf("PLL is not locked - Failed to initialize lane %d\n",  in comphy_a3700_init()