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/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dsnps-dw-apb-uart.txt4 - compatible : "snps,dw-apb-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : should contain uart interrupt.
10 - clock-frequency : the input clock frequency for the UART.
11 - clocks : phandle to the input clock
14 - clock-names: tuple listing input clock names.
18 - snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
21 - resets : phandle to the parent reset controller.
22 - reg-shift : quantity to shift the register offsets by. If this property is
24 - reg-io-width : the size (in bytes) of the IO accesses that should be
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
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H A Dcdns,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
15 - description: UART controller for Zynq-7xxx SoC
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
21 - const: xlnx,zynqmp-uart
22 - const: cdns,uart-r1p12
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/openbmc/linux/drivers/hwtracing/intel_th/
H A Dgth.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2015 Intel Corporation.
42 REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
45 REG_GTH_DESTOVR = 0xdc, /* Destination override */
53 /* Common Capture Sequencer (CTS) registers */
66 /* waiting for Trigger status to assert for CTS */
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/vk-gl-cts/
H A Dkhronos-cts.inc1 LICENSE = "Apache-2.0"
4 SRC_URI = "git://github.com/KhronosGroup/VK-GL-CTS.git;protocol=https;name=vk-gl-cts;nobranch=1 \
5 file://0001-cmake-Define-WAYLAND_SCANNER-and-WAYLAND_PROTOCOLS_D.patch \
6 file://0001-use-library-sonames-for-linking.patch \
7 file://generate-srcuri.py \
10 SRC_URI:append:libc-musl = "file://fix-musl.patch"
11 SRC_URI:append:toolchain-clang = "file://fix-clang-private-operator.patch"
13 SRCREV_FORMAT = "vk-gl-cts"
17 inherit pkgconfig cmake cmake-qemu features_check python3native
19 UPSTREAM_CHECK_GITTAGREGEX = "${BPN}-(?P<pver>\d+(\.\d+)+)"
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/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
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/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Ddesc.h2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
24 * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
38 * struct ath5k_hw_rx_status - Common hardware RX status descriptor
105 * enum ath5k_phy_error_code - PHY Error codes
113 * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
151 * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor
166 #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */
168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211 0x00800000 /* [5211] virtual end-of-list */
173 (ah->ah_version == AR5K_AR5210 ? \
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/openbmc/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
32 return core->base + HDMI_CORE_AV; in hdmi_av_base()
37 void __iomem *base = core->base; in hdmi4_core_ddc_init()
50 return -ETIMEDOUT; in hdmi4_core_ddc_init()
61 return -ETIMEDOUT; in hdmi4_core_ddc_init()
71 return -ETIMEDOUT; in hdmi4_core_ddc_init()
80 void __iomem *base = core->base; in hdmi4_core_ddc_read()
87 return -ETIMEDOUT; in hdmi4_core_ddc_read()
112 return -EIO; in hdmi4_core_ddc_read()
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/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
33 return core->base + HDMI_CORE_AV; in hdmi_av_base()
38 void __iomem *base = core->base; in hdmi_core_ddc_init()
51 return -ETIMEDOUT; in hdmi_core_ddc_init()
62 return -ETIMEDOUT; in hdmi_core_ddc_init()
72 return -ETIMEDOUT; in hdmi_core_ddc_init()
81 void __iomem *base = core->base; in hdmi_core_ddc_edid()
90 return -ETIMEDOUT; in hdmi_core_ddc_edid()
118 return -EIO; in hdmi_core_ddc_edid()
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/openbmc/linux/drivers/tty/serial/8250/
H A D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
101 /* Override any modem control signals if needed */ in dw8250_modify_msr()
103 value |= d->msr_mask_on; in dw8250_modify_msr()
104 value &= ~d->msr_mask_off; in dw8250_modify_msr()
122 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
123 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
128 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
133 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
137 while (tries--) { in dw8250_check_lcr()
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/openbmc/linux/fs/crypto/
H A Dkeysetup.c1 // SPDX-License-Identifier: GPL-2.0
18 .friendly_name = "AES-256-XTS",
26 .friendly_name = "AES-256-CTS-CBC",
27 .cipher_str = "cts(cbc(aes))",
33 .friendly_name = "AES-128-CBC-ESSIV",
41 .friendly_name = "AES-128-CTS-CBC",
42 .cipher_str = "cts(cbc(aes))",
48 .friendly_name = "SM4-XTS",
56 .friendly_name = "SM4-CTS-CBC",
57 .cipher_str = "cts(cbc(sm4))",
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/openbmc/linux/drivers/net/wireless/ath/ath6kl/
H A Dtarget.h2 * Copyright (c) 2004-2010 Atheros Communications Inc.
161 * Pointer to application-defined area, if any.
175 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags.
189 /* Override Target application start address */
225 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
235 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
251 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
273 * 0xbc - [31:0]: idle timeout in ms
281 /* If non-zero, override values sent to Host in WMI_READY event. */
286 * Percentage of high priority RX traffic to total expected RX traffic -
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/openbmc/linux/drivers/tty/serial/
H A Daltera_uart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * altera_uart.c -- Altera UART driver
5 * Based on mcf.c -- Freescale ColdFire UART driver
7 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
54 #define ALTERA_UART_STATUS_DCTS_MSK 0x0400 /* CTS logic-level change */
55 #define ALTERA_UART_STATUS_CTS_MSK 0x0800 /* CTS logic state */
70 #define ALTERA_UART_CONTROL_DCTS_MSK 0x0400 /* Interrupt on CTS change */
75 * Local per-uart structure.
86 return readl(port->membase + (reg << port->regshift)); in altera_uart_readl()
91 writel(dat, port->membase + (reg << port->regshift)); in altera_uart_writel()
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H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
4 ** serial driver for the Mux console found in some PA-RISC servers.
7 ** (c) Copyright 2002 Hewlett-Packard Company
26 #include <asm/parisc-device.h>
63 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
64 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
67 * get_mux_port_count - Get the number of available ports on the Mux.
73 * are connected. This function can override the IODC and
82 /* If this is the built-in Mux for the K-Class (Eole CAP/MUX), in get_mux_port_count()
86 if(dev->id.hversion == 0x15) in get_mux_port_count()
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/openbmc/linux/drivers/usb/serial/
H A Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
97 result = usb_control_msg(serial->dev, in ark3116_read_reg()
98 usb_rcvctrlpipe(serial->dev, 0), in ark3116_read_reg()
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dtx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
27 * @TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
38 * @TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
73 * enum iwl_tx_cmd_flags - bitmasks for tx_flags in TX command for 22000
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/openbmc/qemu/rust/hw/char/pl011/src/
H A Dlib.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
57 /// ARM DDI 0183G, Table 3-1 p.3-3
82 /// `IrDA` Low-Power Counter Register
121 fn try_from(value: u64) -> Result<Self, Self::Error> { in try_from()
148 //! All PL011 registers are essentially 32-bit wide, but are typed here as
151 //! as a 32-bit register where the unmentioned higher bits are always
162 /// - if the FIFOs are enabled, data written to this location is pushed onto
165 /// - if the FIFOs are not enabled, data is stored in the transmitter
176 /// - if the FIFOs are enabled, the data byte and the 4-bit status (break,
178 /// and overrun) is pushed onto the 12-bit wide receive FIFO
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dmain.c3 * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
50 /* n-mode support capability */
82 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
167 #define BRCMS_PLCP_AUTO -1
172 #define BRCMS_PROTECTION_AUTO -1
199 /* MSC in use,indicates b0-6 holds an mcs */
207 /* bit indicate to override mcs only */
361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] in brcms_basic_rate()
363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; in brcms_basic_rate()
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/openbmc/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
38 #include "dw-hdmi-audio.h"
39 #include "dw-hdmi-cec.h"
40 #include "dw-hdmi.h"
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/openbmc/linux/drivers/gpu/drm/bridge/
H A Dsii9234.c1 // SPDX-License-Identifier: GPL-2.0-or-later
198 struct i2c_client *client = ctx->client[id]; in sii9234_writeb()
200 if (ctx->i2c_error) in sii9234_writeb()
201 return ctx->i2c_error; in sii9234_writeb()
205 dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n", in sii9234_writeb()
207 ctx->i2c_error = ret; in sii9234_writeb()
216 struct i2c_client *client = ctx->client[id]; in sii9234_writebm()
218 if (ctx->i2c_error) in sii9234_writebm()
219 return ctx->i2c_error; in sii9234_writebm()
223 dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n", in sii9234_writebm()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-370.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
31 compatible = "marvell,armada370-mbus", "simple-bus";
39 compatible = "marvell,armada-370-pcie";
43 #address-cells = <3>;
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/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00queue.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
18 #include <linux/dma-mapping.h>
25 struct data_queue *queue = entry->queue; in rt2x00queue_alloc_rxskb()
26 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2x00queue_alloc_rxskb()
37 frame_size = queue->data_size + queue->desc_size + queue->winfo_size; in rt2x00queue_alloc_rxskb()
40 * The payload should be aligned to a 4-byte boundary, in rt2x00queue_alloc_rxskb()
79 skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len, in rt2x00queue_alloc_rxskb()
81 if (unlikely(dma_mapping_error(rt2x00dev->dev, skb_dma))) { in rt2x00queue_alloc_rxskb()
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/openbmc/linux/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
54 This option provides the ability to override the FIPS Module Version.
170 bool "Disable run-time self tests"
173 Disable run-time self tests that normally take place at
177 bool "Enable extra run-time crypto self tests"
180 Enable extra run-time self tests of registered crypto algorithms,
246 menu "Public-key cryptography"
249 tristate "RSA (Rivest-Shamir-Adleman)"
255 RSA (Rivest-Shamir-Adleman) public key algorithm (RFC8017)
258 tristate "DH (Diffie-Hellman)"
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/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
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H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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