1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2010 Atheros Communications Inc. 31b2df407SVasanthakumar Thiagarajan * Copyright (c) 2011 Qualcomm Atheros, Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18bdcd8170SKalle Valo #ifndef TARGET_H 19bdcd8170SKalle Valo #define TARGET_H 20bdcd8170SKalle Valo 21bdcd8170SKalle Valo #define AR6003_BOARD_DATA_SZ 1024 22bdcd8170SKalle Valo #define AR6003_BOARD_EXT_DATA_SZ 768 23fb1ac2efSPrasanna Kumar #define AR6003_BOARD_EXT_DATA_SZ_V2 1024 24bdcd8170SKalle Valo 25d5720e59SKalle Valo #define AR6004_BOARD_DATA_SZ 6144 2631024d99SKevin Fang #define AR6004_BOARD_EXT_DATA_SZ 0 2731024d99SKevin Fang 28ec1461dcSKalle Valo #define RESET_CONTROL_ADDRESS 0x00004000 29bdcd8170SKalle Valo #define RESET_CONTROL_COLD_RST 0x00000100 30bdcd8170SKalle Valo #define RESET_CONTROL_MBOX_RST 0x00000004 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo #define CPU_CLOCK_STANDARD_S 0 33bdcd8170SKalle Valo #define CPU_CLOCK_STANDARD 0x00000003 34bdcd8170SKalle Valo #define CPU_CLOCK_ADDRESS 0x00000020 35bdcd8170SKalle Valo 36bdcd8170SKalle Valo #define CLOCK_CONTROL_ADDRESS 0x00000028 37bdcd8170SKalle Valo #define CLOCK_CONTROL_LF_CLK32_S 2 38bdcd8170SKalle Valo #define CLOCK_CONTROL_LF_CLK32 0x00000004 39bdcd8170SKalle Valo 40bdcd8170SKalle Valo #define SYSTEM_SLEEP_ADDRESS 0x000000c4 41bdcd8170SKalle Valo #define SYSTEM_SLEEP_DISABLE_S 0 42bdcd8170SKalle Valo #define SYSTEM_SLEEP_DISABLE 0x00000001 43bdcd8170SKalle Valo 44bdcd8170SKalle Valo #define LPO_CAL_ADDRESS 0x000000e0 45bdcd8170SKalle Valo #define LPO_CAL_ENABLE_S 20 46bdcd8170SKalle Valo #define LPO_CAL_ENABLE 0x00100000 47bdcd8170SKalle Valo 48fa338be0SVasanthakumar Thiagarajan #define GPIO_PIN9_ADDRESS 0x0000004c 49bdcd8170SKalle Valo #define GPIO_PIN10_ADDRESS 0x00000050 50bdcd8170SKalle Valo #define GPIO_PIN11_ADDRESS 0x00000054 51bdcd8170SKalle Valo #define GPIO_PIN12_ADDRESS 0x00000058 52bdcd8170SKalle Valo #define GPIO_PIN13_ADDRESS 0x0000005c 53bdcd8170SKalle Valo 54bdcd8170SKalle Valo #define HOST_INT_STATUS_ADDRESS 0x00000400 55bdcd8170SKalle Valo #define HOST_INT_STATUS_ERROR_S 7 56bdcd8170SKalle Valo #define HOST_INT_STATUS_ERROR 0x00000080 57bdcd8170SKalle Valo 58bdcd8170SKalle Valo #define HOST_INT_STATUS_CPU_S 6 59bdcd8170SKalle Valo #define HOST_INT_STATUS_CPU 0x00000040 60bdcd8170SKalle Valo 61bdcd8170SKalle Valo #define HOST_INT_STATUS_COUNTER_S 4 62bdcd8170SKalle Valo #define HOST_INT_STATUS_COUNTER 0x00000010 63bdcd8170SKalle Valo 64bdcd8170SKalle Valo #define CPU_INT_STATUS_ADDRESS 0x00000401 65bdcd8170SKalle Valo 66bdcd8170SKalle Valo #define ERROR_INT_STATUS_ADDRESS 0x00000402 67bdcd8170SKalle Valo #define ERROR_INT_STATUS_WAKEUP_S 2 68bdcd8170SKalle Valo #define ERROR_INT_STATUS_WAKEUP 0x00000004 69bdcd8170SKalle Valo 70bdcd8170SKalle Valo #define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 71bdcd8170SKalle Valo #define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 72bdcd8170SKalle Valo 73bdcd8170SKalle Valo #define ERROR_INT_STATUS_TX_OVERFLOW_S 0 74bdcd8170SKalle Valo #define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 75bdcd8170SKalle Valo 76bdcd8170SKalle Valo #define COUNTER_INT_STATUS_ADDRESS 0x00000403 77bdcd8170SKalle Valo #define COUNTER_INT_STATUS_COUNTER_S 0 78bdcd8170SKalle Valo #define COUNTER_INT_STATUS_COUNTER 0x000000ff 79bdcd8170SKalle Valo 80bdcd8170SKalle Valo #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 81bdcd8170SKalle Valo 82bdcd8170SKalle Valo #define INT_STATUS_ENABLE_ADDRESS 0x00000418 83bdcd8170SKalle Valo #define INT_STATUS_ENABLE_ERROR_S 7 84bdcd8170SKalle Valo #define INT_STATUS_ENABLE_ERROR 0x00000080 85bdcd8170SKalle Valo 86bdcd8170SKalle Valo #define INT_STATUS_ENABLE_CPU_S 6 87bdcd8170SKalle Valo #define INT_STATUS_ENABLE_CPU 0x00000040 88bdcd8170SKalle Valo 89bdcd8170SKalle Valo #define INT_STATUS_ENABLE_INT_S 5 90bdcd8170SKalle Valo #define INT_STATUS_ENABLE_INT 0x00000020 91bdcd8170SKalle Valo #define INT_STATUS_ENABLE_COUNTER_S 4 92bdcd8170SKalle Valo #define INT_STATUS_ENABLE_COUNTER 0x00000010 93bdcd8170SKalle Valo 94bdcd8170SKalle Valo #define INT_STATUS_ENABLE_MBOX_DATA_S 0 95bdcd8170SKalle Valo #define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f 96bdcd8170SKalle Valo 97bdcd8170SKalle Valo #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 98bdcd8170SKalle Valo #define CPU_INT_STATUS_ENABLE_BIT_S 0 99bdcd8170SKalle Valo #define CPU_INT_STATUS_ENABLE_BIT 0x000000ff 100bdcd8170SKalle Valo 101bdcd8170SKalle Valo #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a 102bdcd8170SKalle Valo #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 103bdcd8170SKalle Valo #define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 104bdcd8170SKalle Valo 105bdcd8170SKalle Valo #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 106bdcd8170SKalle Valo #define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 107bdcd8170SKalle Valo 108bdcd8170SKalle Valo #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b 109bdcd8170SKalle Valo #define COUNTER_INT_STATUS_ENABLE_BIT_S 0 110bdcd8170SKalle Valo #define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff 111bdcd8170SKalle Valo 112bdcd8170SKalle Valo #define COUNT_ADDRESS 0x00000420 113bdcd8170SKalle Valo 114bdcd8170SKalle Valo #define COUNT_DEC_ADDRESS 0x00000440 115bdcd8170SKalle Valo 116bdcd8170SKalle Valo #define WINDOW_DATA_ADDRESS 0x00000474 117bdcd8170SKalle Valo #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 118bdcd8170SKalle Valo #define WINDOW_READ_ADDR_ADDRESS 0x0000047c 119bdcd8170SKalle Valo #define CPU_DBG_SEL_ADDRESS 0x00000483 120bdcd8170SKalle Valo #define CPU_DBG_ADDRESS 0x00000484 121bdcd8170SKalle Valo 122bdcd8170SKalle Valo #define LOCAL_SCRATCH_ADDRESS 0x000000c0 123bdcd8170SKalle Valo #define ATH6KL_OPTION_SLEEP_DISABLE 0x08 124bdcd8170SKalle Valo 125bdcd8170SKalle Valo #define RTC_BASE_ADDRESS 0x00004000 126bdcd8170SKalle Valo #define GPIO_BASE_ADDRESS 0x00014000 127bdcd8170SKalle Valo #define MBOX_BASE_ADDRESS 0x00018000 128bdcd8170SKalle Valo #define ANALOG_INTF_BASE_ADDRESS 0x0001c000 129bdcd8170SKalle Valo 130bdcd8170SKalle Valo /* real name of the register is unknown */ 131bdcd8170SKalle Valo #define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo #define SM(f, v) (((v) << f##_S) & f) 134bdcd8170SKalle Valo #define MS(f, v) (((v) & f) >> f##_S) 135bdcd8170SKalle Valo 136bdcd8170SKalle Valo /* 137bdcd8170SKalle Valo * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 138bdcd8170SKalle Valo * host_interest structure. 139bdcd8170SKalle Valo * 140bdcd8170SKalle Valo * Host Interest is shared between Host and Target in order to coordinate 141bdcd8170SKalle Valo * between the two, and is intended to remain constant (with additions only 142bdcd8170SKalle Valo * at the end). 143bdcd8170SKalle Valo */ 14431024d99SKevin Fang #define ATH6KL_AR6003_HI_START_ADDR 0x00540600 14531024d99SKevin Fang #define ATH6KL_AR6004_HI_START_ADDR 0x00400800 146bdcd8170SKalle Valo 147bdcd8170SKalle Valo /* 148bdcd8170SKalle Valo * These are items that the Host may need to access 149bdcd8170SKalle Valo * via BMI or via the Diagnostic Window. The position 150bdcd8170SKalle Valo * of items in this structure must remain constant. 151bdcd8170SKalle Valo * across firmware revisions! 152bdcd8170SKalle Valo * 153bdcd8170SKalle Valo * Types for each item must be fixed size across target and host platforms. 154bdcd8170SKalle Valo * The structure is used only to calculate offset for each register with 155bdcd8170SKalle Valo * HI_ITEM() macro, no values are stored to it. 156bdcd8170SKalle Valo * 157bdcd8170SKalle Valo * More items may be added at the end. 158bdcd8170SKalle Valo */ 159bdcd8170SKalle Valo struct host_interest { 160bdcd8170SKalle Valo /* 161bdcd8170SKalle Valo * Pointer to application-defined area, if any. 162bdcd8170SKalle Valo * Set by Target application during startup. 163bdcd8170SKalle Valo */ 164bdcd8170SKalle Valo u32 hi_app_host_interest; /* 0x00 */ 165bdcd8170SKalle Valo 166bdcd8170SKalle Valo /* Pointer to register dump area, valid after Target crash. */ 167bdcd8170SKalle Valo u32 hi_failure_state; /* 0x04 */ 168bdcd8170SKalle Valo 169bdcd8170SKalle Valo /* Pointer to debug logging header */ 170bdcd8170SKalle Valo u32 hi_dbglog_hdr; /* 0x08 */ 171bdcd8170SKalle Valo 172bdcd8170SKalle Valo u32 hi_unused1; /* 0x0c */ 173bdcd8170SKalle Valo 174bdcd8170SKalle Valo /* 175bdcd8170SKalle Valo * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. 176bdcd8170SKalle Valo * Can be used by application rather than by OS. 177bdcd8170SKalle Valo */ 178bdcd8170SKalle Valo u32 hi_option_flag; /* 0x10 */ 179bdcd8170SKalle Valo 180bdcd8170SKalle Valo /* 181bdcd8170SKalle Valo * Boolean that determines whether or not to 182bdcd8170SKalle Valo * display messages on the serial port. 183bdcd8170SKalle Valo */ 184bdcd8170SKalle Valo u32 hi_serial_enable; /* 0x14 */ 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo /* Start address of DataSet index, if any */ 187bdcd8170SKalle Valo u32 hi_dset_list_head; /* 0x18 */ 188bdcd8170SKalle Valo 189bdcd8170SKalle Valo /* Override Target application start address */ 190bdcd8170SKalle Valo u32 hi_app_start; /* 0x1c */ 191bdcd8170SKalle Valo 192bdcd8170SKalle Valo /* Clock and voltage tuning */ 193bdcd8170SKalle Valo u32 hi_skip_clock_init; /* 0x20 */ 194bdcd8170SKalle Valo u32 hi_core_clock_setting; /* 0x24 */ 195bdcd8170SKalle Valo u32 hi_cpu_clock_setting; /* 0x28 */ 196bdcd8170SKalle Valo u32 hi_system_sleep_setting; /* 0x2c */ 197bdcd8170SKalle Valo u32 hi_xtal_control_setting; /* 0x30 */ 198bdcd8170SKalle Valo u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 199bdcd8170SKalle Valo u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 200bdcd8170SKalle Valo u32 hi_ref_voltage_trim_setting; /* 0x3c */ 201bdcd8170SKalle Valo u32 hi_clock_info; /* 0x40 */ 202bdcd8170SKalle Valo 203bdcd8170SKalle Valo /* 204bdcd8170SKalle Valo * Flash configuration overrides, used only 205bdcd8170SKalle Valo * when firmware is not executing from flash. 206bdcd8170SKalle Valo * (When using flash, modify the global variables 207bdcd8170SKalle Valo * with equivalent names.) 208bdcd8170SKalle Valo */ 209bdcd8170SKalle Valo u32 hi_bank0_addr_value; /* 0x44 */ 210bdcd8170SKalle Valo u32 hi_bank0_read_value; /* 0x48 */ 211bdcd8170SKalle Valo u32 hi_bank0_write_value; /* 0x4c */ 212bdcd8170SKalle Valo u32 hi_bank0_config_value; /* 0x50 */ 213bdcd8170SKalle Valo 214bdcd8170SKalle Valo /* Pointer to Board Data */ 215bdcd8170SKalle Valo u32 hi_board_data; /* 0x54 */ 216bdcd8170SKalle Valo u32 hi_board_data_initialized; /* 0x58 */ 217bdcd8170SKalle Valo 218bdcd8170SKalle Valo u32 hi_dset_ram_index_tbl; /* 0x5c */ 219bdcd8170SKalle Valo 220bdcd8170SKalle Valo u32 hi_desired_baud_rate; /* 0x60 */ 221bdcd8170SKalle Valo u32 hi_dbglog_config; /* 0x64 */ 222bdcd8170SKalle Valo u32 hi_end_ram_reserve_sz; /* 0x68 */ 223bdcd8170SKalle Valo u32 hi_mbox_io_block_sz; /* 0x6c */ 224bdcd8170SKalle Valo 225bdcd8170SKalle Valo u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 226bdcd8170SKalle Valo u32 hi_mbox_isr_yield_limit; /* 0x74 */ 227bdcd8170SKalle Valo 228bdcd8170SKalle Valo u32 hi_refclk_hz; /* 0x78 */ 229bdcd8170SKalle Valo u32 hi_ext_clk_detected; /* 0x7c */ 230bdcd8170SKalle Valo u32 hi_dbg_uart_txpin; /* 0x80 */ 231bdcd8170SKalle Valo u32 hi_dbg_uart_rxpin; /* 0x84 */ 232bdcd8170SKalle Valo u32 hi_hci_uart_baud; /* 0x88 */ 233bdcd8170SKalle Valo u32 hi_hci_uart_pin_assignments; /* 0x8C */ 234bdcd8170SKalle Valo /* 235bdcd8170SKalle Valo * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts 236bdcd8170SKalle Valo * pin 237bdcd8170SKalle Valo */ 238bdcd8170SKalle Valo u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 239bdcd8170SKalle Valo u32 hi_hci_uart_baud_step_val; /* 0x94 */ 240bdcd8170SKalle Valo 241bdcd8170SKalle Valo u32 hi_allocram_start; /* 0x98 */ 242bdcd8170SKalle Valo u32 hi_allocram_sz; /* 0x9c */ 243bdcd8170SKalle Valo u32 hi_hci_bridge_flags; /* 0xa0 */ 244bdcd8170SKalle Valo u32 hi_hci_uart_support_pins; /* 0xa4 */ 245bdcd8170SKalle Valo /* 246bdcd8170SKalle Valo * NOTE: byte [0] = RESET pin (bit 7 is polarity), 247bdcd8170SKalle Valo * bytes[1]..bytes[3] are for future use 248bdcd8170SKalle Valo */ 249bdcd8170SKalle Valo u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 250bdcd8170SKalle Valo /* 251bdcd8170SKalle Valo * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 252bdcd8170SKalle Valo * [31:16]: wakeup timeout in ms 253bdcd8170SKalle Valo */ 254bdcd8170SKalle Valo 255bdcd8170SKalle Valo /* Pointer to extended board data */ 256bdcd8170SKalle Valo u32 hi_board_ext_data; /* 0xac */ 257bdcd8170SKalle Valo u32 hi_board_ext_data_config; /* 0xb0 */ 258bdcd8170SKalle Valo 259bdcd8170SKalle Valo /* 260bdcd8170SKalle Valo * Bit [0] : valid 261bdcd8170SKalle Valo * Bit[31:16: size 262bdcd8170SKalle Valo */ 263bdcd8170SKalle Valo /* 264bdcd8170SKalle Valo * hi_reset_flag is used to do some stuff when target reset. 265bdcd8170SKalle Valo * such as restore app_start after warm reset or 266bdcd8170SKalle Valo * preserve host Interest area, or preserve ROM data, literals etc. 267bdcd8170SKalle Valo */ 268bdcd8170SKalle Valo u32 hi_reset_flag; /* 0xb4 */ 269bdcd8170SKalle Valo /* indicate hi_reset_flag is valid */ 270bdcd8170SKalle Valo u32 hi_reset_flag_valid; /* 0xb8 */ 271bdcd8170SKalle Valo u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 272bdcd8170SKalle Valo /* 273bdcd8170SKalle Valo * 0xbc - [31:0]: idle timeout in ms 274bdcd8170SKalle Valo */ 275bdcd8170SKalle Valo /* ACS flags */ 276bdcd8170SKalle Valo u32 hi_acs_flags; /* 0xc0 */ 277bdcd8170SKalle Valo u32 hi_console_flags; /* 0xc4 */ 278bdcd8170SKalle Valo u32 hi_nvram_state; /* 0xc8 */ 279bdcd8170SKalle Valo u32 hi_option_flag2; /* 0xcc */ 280bdcd8170SKalle Valo 281bdcd8170SKalle Valo /* If non-zero, override values sent to Host in WMI_READY event. */ 282bdcd8170SKalle Valo u32 hi_sw_version_override; /* 0xd0 */ 283bdcd8170SKalle Valo u32 hi_abi_version_override; /* 0xd4 */ 284bdcd8170SKalle Valo 285bdcd8170SKalle Valo /* 286bdcd8170SKalle Valo * Percentage of high priority RX traffic to total expected RX traffic - 287bdcd8170SKalle Valo * applicable only to ar6004 288bdcd8170SKalle Valo */ 289bdcd8170SKalle Valo u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 290bdcd8170SKalle Valo 291bdcd8170SKalle Valo /* test applications flags */ 292bdcd8170SKalle Valo u32 hi_test_apps_related; /* 0xdc */ 293bdcd8170SKalle Valo /* location of test script */ 294bdcd8170SKalle Valo u32 hi_ota_testscript; /* 0xe0 */ 295bdcd8170SKalle Valo /* location of CAL data */ 296bdcd8170SKalle Valo u32 hi_cal_data; /* 0xe4 */ 297bdcd8170SKalle Valo /* Number of packet log buffers */ 298bdcd8170SKalle Valo u32 hi_pktlog_num_buffers; /* 0xe8 */ 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo } __packed; 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo #define HI_ITEM(item) offsetof(struct host_interest, item) 303bdcd8170SKalle Valo 304bdcd8170SKalle Valo #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo #define HI_OPTION_FW_MODE_IBSS 0x0 307bdcd8170SKalle Valo #define HI_OPTION_FW_MODE_BSS_STA 0x1 308bdcd8170SKalle Valo #define HI_OPTION_FW_MODE_AP 0x2 309bdcd8170SKalle Valo 3106bbc7c35SJouni Malinen #define HI_OPTION_FW_SUBMODE_NONE 0x0 3116bbc7c35SJouni Malinen #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 3126bbc7c35SJouni Malinen #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 3136bbc7c35SJouni Malinen #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 3146bbc7c35SJouni Malinen 315bdcd8170SKalle Valo #define HI_OPTION_NUM_DEV_SHIFT 0x9 316bdcd8170SKalle Valo 317bdcd8170SKalle Valo #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 318bdcd8170SKalle Valo 319bdcd8170SKalle Valo /* Fw Mode/SubMode Mask 320bdcd8170SKalle Valo |------------------------------------------------------------------------------| 321bdcd8170SKalle Valo | SUB | SUB | SUB | SUB | | | | 322bdcd8170SKalle Valo | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| 323bdcd8170SKalle Valo | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 324bdcd8170SKalle Valo |------------------------------------------------------------------------------| 325bdcd8170SKalle Valo */ 3267b85832dSVasanthakumar Thiagarajan #define HI_OPTION_FW_MODE_BITS 0x2 327bdcd8170SKalle Valo #define HI_OPTION_FW_MODE_SHIFT 0xC 3287b85832dSVasanthakumar Thiagarajan 3297b85832dSVasanthakumar Thiagarajan #define HI_OPTION_FW_SUBMODE_BITS 0x2 3306bbc7c35SJouni Malinen #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 331bdcd8170SKalle Valo 332bdcd8170SKalle Valo /* Convert a Target virtual address into a Target physical address */ 33331024d99SKevin Fang #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 33431024d99SKevin Fang #define AR6004_VTOP(vaddr) (vaddr) 33531024d99SKevin Fang 33631024d99SKevin Fang #define TARG_VTOP(target_type, vaddr) \ 33731024d99SKevin Fang (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ 33831024d99SKevin Fang (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0)) 339bdcd8170SKalle Valo 340bdf5396bSKalle Valo #define ATH6KL_FWLOG_PAYLOAD_SIZE 1500 341bdf5396bSKalle Valo 342bc07ddb2SKalle Valo struct ath6kl_dbglog_buf { 343bc07ddb2SKalle Valo __le32 next; 344bc07ddb2SKalle Valo __le32 buffer_addr; 345bc07ddb2SKalle Valo __le32 bufsize; 346bc07ddb2SKalle Valo __le32 length; 347bc07ddb2SKalle Valo __le32 count; 348bc07ddb2SKalle Valo __le32 free; 349bc07ddb2SKalle Valo } __packed; 350bc07ddb2SKalle Valo 351bc07ddb2SKalle Valo struct ath6kl_dbglog_hdr { 352bc07ddb2SKalle Valo __le32 dbuf_addr; 353bc07ddb2SKalle Valo __le32 dropped; 354bc07ddb2SKalle Valo } __packed; 355bc07ddb2SKalle Valo 356bdcd8170SKalle Valo #endif 357