Home
last modified time | relevance | path

Searched full:cs1 (Results 1 – 25 of 364) sorted by relevance

12345678910>>...15

/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
56 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ in make_cs1_contiguous()
147 * setup CS1. in do_sdrc_init()
172 write_sdrc_timings(CS1, sdrc_actim_base1, &timings); in do_sdrc_init()
180 * both CS0 and CS1 (such as some older versions of x-loader) in do_sdrc_init()
181 * so we may be asked now to setup CS1. in do_sdrc_init()
183 if (cs == CS1) { in do_sdrc_init()
210 do_sdrc_init(CS1, NOT_EARLY); in dram_init()
211 size1 = get_sdr_cs_size(CS1); in dram_init()
223 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
[all …]
H A Demif4.c133 * If a second bank of DDR is attached to CS1 this is in dram_init()
138 size1 = get_sdr_cs_size(CS1); in dram_init()
149 size1 = get_sdr_cs_size(CS1); in dram_init_banksize()
153 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-sx93246 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
19 while CS1 and CS2 are used as shields.
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
25 [PH3], CS1 and CS2 are measured (combo mode):
H A Dsysfs-class-watchdog111 chip at CS1.
114 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
115 CS1->CS1).
121 For alternate boot mode (booted from CS1 due to wdt2
/openbmc/u-boot/drivers/ddr/fsl/
H A Doptions.c50 { /* cs1 */
77 { /* cs1 */
106 { /* cs1 */
133 { /* cs1 */
193 { /* cs1 */
253 { /* cs1 */
280 { /* cs1 */
307 { /* cs1 */
336 { /* cs1 */
363 { /* cs1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt55 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
H A Dmediatek,mt76x8-pinctrl.yaml42 spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt,
83 spi cs1, spis, uart0, uart1, uart2, wdt, wled_an,
275 enum: [gpio, refclk, spi cs1]
334 const: spi cs1
338 enum: [spi cs1]
429 enum: [i2c, spi cs1, uart0]
H A Dmarvell,armada-370-pinctrl.txt27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
28 sata1(prsnt), spi1(cs1)
70 spi0(cs1)
80 mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
83 pcie(clkreq0), spi1(cs1)
95 mpp64 64 gpio, spi0(miso), spi0(cs1)
H A Dmarvell,armada-38x-pinctrl.txt30 mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
39 mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
44 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
73 mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
H A Dmarvell,armada-375-pinctrl.txt16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
51 mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
H A Dmarvell,armada-98dx3236-pinctrl.txt18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt39 - cs1-used : Have this property if CS1 of this EMIF
41 part attached to CS1, it should be the same type as the one on CS0,
66 cs1-used;
/openbmc/linux/arch/sh/boards/
H A Dboard-urquell.c35 * CS1 : SRAM, registers, LAN, PCMCIA
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-fsl-lpspi.yaml52 fsl,spi-only-use-cs1-sel:
55 i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
92 fsl,spi-only-use-cs1-sel;
/openbmc/u-boot/drivers/watchdog/
H A Dulp_wdog.c14 u8 cs1; member
74 writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ in hw_watchdog_init()
90 writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ in reset_cpu()
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c33 #define CS1 gpio.aux[1] macro
106 if (!par->CS1) { in verify_gpios()
108 "Missing info about 'cs1' gpio. Aborting.\n"); in verify_gpios()
134 } else if (strcasecmp(gpio->name, "cs1") == 0) { in request_gpios_match()
136 par->CS1 = gpio->gpio; in request_gpios_match()
183 /* cs1 */ in write_reg8_bus8()
185 gpiod_set_value(par->CS1, 1); in write_reg8_bus8()
189 gpiod_set_value(par->CS1, 0); in write_reg8_bus8()
388 gpiod_set_value(par->CS1, 0); in write_vmem()
/openbmc/linux/sound/soc/intel/catpt/
H A Ddsp.c222 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); in catpt_dsp_stall()
224 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_stall()
234 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); in catpt_dsp_reset()
236 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_reset()
265 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; in catpt_dsp_select_lpclock()
298 catpt_updatel_shim(cdev, CS1, mask, val); in catpt_dsp_select_lpclock()
329 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); in catpt_dsp_set_regs_defaults()
366 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_down()
428 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in catpt_dsp_power_up()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c23 u8 cs1; member
37 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
231 para->cs1 = 0; in mctl_channel_init()
266 /* Retry 16 bit bus-width with CS1 set */ in mctl_channel_init()
267 para->cs1 = 1; in mctl_channel_init()
275 para->cs1 = 0; in mctl_channel_init()
335 .cs1 = 0, in sunxi_dram_init()
H A Ddram_sun8i_a83t.c21 u8 cs1; member
36 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
314 para->cs1 = 0; in mctl_channel_init()
358 /* Retry 16 bit bus-width with CS1 set */ in mctl_channel_init()
359 para->cs1 = 1; in mctl_channel_init()
367 para->cs1 = 0; in mctl_channel_init()
433 .cs1 = 0, in sunxi_dram_init()
/openbmc/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9310.yaml56 0 1 - CS0 + CS1
57 1 2 - CS1 + CS2 (default)
58 0 1 2 3 - CS0 + CS1 + CS2 + CS3
/openbmc/u-boot/board/renesas/rsk7269/
H A Dlowlevel_init.S50 write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
66 /* Configure ethernet (CS1) */
69 write16 PFCR2_A, PFCR2_D /* CS1# */
/openbmc/linux/drivers/watchdog/
H A Daspeed_wdt.c250 * after booting from the alternate chip at CS1.
252 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
257 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
/openbmc/linux/arch/hexagon/kernel/
H A Dptrace.c65 membuf_store(&to, regs->cs1); in genregs_get()
113 INEXT(&regs->cs1, cs1); in genregs_set()
H A Dsignal.c55 err |= __put_user(regs->cs1, &sc->sc_regs.cs1); in setup_sigcontext()
85 err |= __get_user(regs->cs1, &sc->sc_regs.cs1); in restore_sigcontext()

12345678910>>...15