/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynosautov9-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source 7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as 11 #include "exynos-pinctrl.h" 14 gpa0: gpa0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 17 interrupt-controller; 18 #interrupt-cells = <2>; 19 interrupt-parent = <&gic>; [all …]
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/openbmc/linux/arch/arm/boot/dts/microchip/ |
H A D | at91-sama5d3_eds.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet 10 /dts-v1/; 15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36", 19 stdout-path = "serial0:115200n8"; 22 gpio-keys { 23 compatible = "gpio-keys"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_key_gpio>; 28 button-3 { [all …]
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H A D | lan966x-kontron-kswitch-d10-mmt.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include "dt-bindings/phy/phy-lan966x-serdes.h" 16 stdout-path = "serial0:115200n8"; 19 gpio-restart { 20 compatible = "gpio-restart"; 21 pinctrl-0 = <&reset_pins>; 22 pinctrl-names = "default"; 29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; 33 pinctrl-0 = <&usart0_pins>; [all …]
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H A D | at91-sama5d3_xplained.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board 8 /dts-v1/; 10 #include <dt-bindings/input/input.h> 14 compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; 17 stdout-path = "serial0:115200n8"; 26 clock-frequency = <32768>; 30 clock-frequency = <12000000>; 37 …pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd… 38 vmmc-supply = <&vcc_mmc0_reg>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx27-eukrea-cpuimx27.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 /dts-v1/; 18 clk14745600: clk-uart { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <14745600>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_fec>; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_i2c1>; [all …]
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H A D | imx6qdl-rex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 13 stdout-path = &uart1; 16 reg_3p3v: regulator-3p3v { 17 compatible = "regulator-fixed"; 18 regulator-name = "3P3V"; 19 regulator-min-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>; 21 regulator-always-on; [all …]
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H A D | imx6q-prti6q.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 6 /dts-v1/; 8 #include "imx6qdl-prti6q.dtsi" 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/sound/fsl-imx-audmux.h> 21 backlight_lcd: backlight-lcd { 22 compatible = "pwm-backlight"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_backlight>; 26 brightness-levels = <0 16 64 255>; [all …]
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H A D | imx6q-evi.dts | 4 * This file is dual-licensed: you can use it either under the terms 44 /dts-v1/; 46 #include <dt-bindings/gpio/gpio.h> 47 #include <dt-bindings/interrupt-controller/irq.h> 51 compatible = "uniwest,imx6q-evi", "fsl,imx6q"; 58 reg_usbh1_vbus: regulator-usbhubreset { 59 compatible = "regulator-fixed"; 60 regulator-name = "usbh1_vbus"; 61 regulator-min-microvolt = <5000000>; 62 regulator-max-microvolt = <5000000>; [all …]
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H A D | imx6dl-prtrvt.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 6 /dts-v1/; 8 #include "imx6qdl-prti6q.dtsi" 9 #include <dt-bindings/leds/common.h> 21 compatible = "gpio-leds"; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&pinctrl_leds>; 25 led-debug0 { 28 linux,default-trigger = "heartbeat"; 34 pinctrl-names = "default"; [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap3-igep.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 /dts-v1/; 19 stdout-path = &uart3; 23 compatible = "ti,omap-twl4030"; 28 vdd33: regulator-vdd33 { 29 compatible = "regulator-fixed"; 30 regulator-name = "vdd33"; 31 regulator-always-on; 37 gpmc_pins: gpmc-pins { 38 pinctrl-single,pins = < [all …]
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H A D | omap3-lilly-a83x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 model = "INCOstartec LILLY-A83X module (DM3730)"; 10 compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; 22 compatible = "gpio-leds"; 25 label = "lilly-a83x::led1"; 27 linux,default-trigger = "default-on"; 33 compatible = "ti,omap-twl4030"; 34 ti,model = "lilly-a83x"; 40 compatible = "regulator-fixed"; 41 regulator-name = "VCC3"; [all …]
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H A D | omap4-duovero-parlor.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 5 /dts-v1/; 7 #include "omap4-duovero.dtsi" 9 #include <dt-bindings/input/input.h> 13 compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; 20 compatible = "gpio-leds"; 24 linux,default-trigger = "heartbeat"; 29 compatible = "gpio-keys"; 30 #address-cells = <1>; 31 #size-cells = <0>; [all …]
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H A D | omap3-sb-t35.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 10 powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ 12 pinctrl-names = "default"; 13 pinctrl-0 = <&tfp410_pins>; 16 #address-cells = <1>; 17 #size-cells = <0>; 23 remote-endpoint = <&dpi_out>; 31 remote-endpoint = <&dvi_connector_in>; 37 dvi0: dvi-connector { [all …]
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H A D | logicpd-torpedo-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 #include <dt-bindings/input/input.h> 7 stdout-path = &uart1; 12 cpu0-supply = <&vcc>; 22 compatible = "gpio-leds"; 23 led-user0 { 26 linux,default-trigger = "none"; 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <26000000>; [all …]
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H A D | am335x-nano.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ 5 /dts-v1/; 15 cpu0-supply = <&dcdc2_reg>; 25 compatible = "gpio-leds"; 30 default-state = "off"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&misc_pins>; 39 misc_pins: misc-pins { 40 pinctrl-single,pins = < [all …]
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H A D | omap3-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 /dts-v1/; 8 #include "omap3-evm-common.dtsi" 9 #include "omap3-evm-processor-common.dtsi" 13 compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&hsusb2_2_pins>; 20 ehci_phy_pins: ehci-phy-pins { 21 pinctrl-single,pins = < [all …]
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H A D | omap3-evm-37xx.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 /dts-v1/; 8 #include "omap3-evm-common.dtsi" 9 #include "omap3-evm-processor-common.dtsi" 13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&hsusb2_2_pins>; 20 ehci_phy_pins: ehci-phy-pins { 21 pinctrl-single,pins = < [all …]
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H A D | dm8148-evm.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 2 /dts-v1/; 5 #include <dt-bindings/interrupt-controller/irq.h> 9 compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814"; 18 compatible = "regulator-fixed"; 19 regulator-name = "vmmcsd_fixed"; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 26 phy-handle = <ðphy0>; 27 phy-mode = "rgmii-id"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-zc1751-xm016-dc2.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 19 model = "ZynqMP zc1751-xm016-dc2 RevA"; 20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7280-idp-ec-h1.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; 12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; 15 compatible = "google,cros-ec-spi"; 17 interrupt-parent = <&tlmm>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&ap_ec_int_l>; 21 spi-max-frequency = <3000000>; 24 compatible = "google,cros-ec-pwm"; 25 #pwm-cells = <1>; [all …]
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H A D | qdu1000.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/dma/qcom-gpi.h> 9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 interrupt-parent = <&intc>; 17 #address-cells = <2>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | omap3-igep.dtsi | 11 /dts-v1/; 22 stdout-path = &uart3; 26 compatible = "ti,omap-twl4030"; 31 vdd33: regulator-vdd33 { 32 compatible = "regulator-fixed"; 33 regulator-name = "vdd33"; 34 regulator-always-on; 41 pinctrl-single,pins = < 48 pinctrl-single,pins = < 55 pinctrl-single,pins = < [all …]
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/openbmc/linux/arch/arm/boot/dts/intel/pxa/ |
H A D | pxa300-raumfeld-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/interrupt-controller/irq.h> 10 hw-revision = <0>; 14 stdout-path = &ffuart; 22 reg_3v3: regulator-3v3 { 23 compatible = "regulator-fixed"; 24 regulator-name = "3v3-fixed-supply"; 25 regulator-min-microvolt = <3300000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc4337-ciaa.dts | 2 * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar) 4 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar 9 * Released under the terms of 3-clause BSD License 12 /dts-v1/; 17 #include "dt-bindings/gpio/gpio.h" 30 stdout-path = &uart2; 40 enet_rmii_pins: enet-rmii-pins { 42 pins = "p1_15", "p0_0"; 44 slew-rate = <1>; 45 bias-disable; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, 16 - Julius Werner <jwerner@chromium.org> 21 - jedec,lpddr2-channel 22 - jedec,lpddr3-channel 23 - jedec,lpddr4-channel 24 - jedec,lpddr5-channel [all …]
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