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12

/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dgoogle,cros-ec-i2c-tunnel.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: I2C bus that tunnels through the ChromeOS EC (cros-ec)
11 - Doug Anderson <dianders@chromium.org>
12 - Benson Leung <bleung@chromium.org>
15 On some ChromeOS board designs we've got a connection to the EC
17 other side of the EC (like a battery and PMIC). To get access to
18 those devices we need to tunnel our i2c commands through the EC.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dgoogle,cros-ec-anx7688.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
10 - Nicolas Boichat <drinkcat@chromium.org>
13 ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
16 (See google,cros-ec.yaml). It is accessed using I2C tunneling through
17 the EC and therefore its node should be a child of an EC I2C tunnel node
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
14 Google's ChromeOS EC is a microcontroller which talks to the AP and
16 The EC can be connected through various interfaces (I2C, SPI, and others)
22 - description:
23 For implementations of the EC connected through I2C.
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-cros-ec-tunnel.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Expose an I2C passthrough to the ChromeOS EC.
8 #include <linux/i2c.h>
17 * struct ec_i2c_device - Driver data for I2C tunnel
20 * @adap: I2C adapter
21 * @ec: Pointer to EC device
22 * @remote_bus: The EC bus number we tunnel to on the other side.
30 struct cros_ec_device *ec; member
39 * ec_i2c_count_message - Count bytes needed for ec_i2c_construct_message
41 * @i2c_msgs: The i2c messages to read
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
14 cros_ec: ec@0 {
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
[all …]
H A Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
12 #include "rk3288-veyron-analog-audio.dtsi"
13 #include "rk3288-veyron-edp.dtsi"
14 #include "rk3288-veyron-sdmmc.dtsi"
22 gpio-charger {
23 compatible = "gpio-charger";
24 charger-type = "mains";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288-veyron.dtsi"
19 gpio_keys: gpio-keys {
20 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
25 linux,input-type = <5>; /* EV_SW */
26 debounce-interval = <1>;
27 gpio-key,wakeup;
31 gpio-charger {
[all …]
H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
14 cpu-model = "Exynos5800";
16 compatible = "google,pit-rev#", "google,pit",
20 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21 hwid = "PIT TEST A-A 7848";
22 lazy-init = <1>;
28 pmic = "/i2c@12CA0000";
33 compatible = "pwm-backlight";
[all …]
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
29 pmic = "/i2c@12CA0000";
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
[all …]
H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
6 rtc0 = "/i2c@7000d000/pmic@40";
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
50 i2c@7000c000 {
52 clock-frequency = <100000>;
[all …]
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
20 i2c0 = "/i2c@12C60000";
21 i2c1 = "/i2c@12C70000";
22 i2c2 = "/i2c@12C80000";
23 i2c3 = "/i2c@12C90000";
24 i2c4 = "/i2c@12CA0000";
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
46 ppvar_sys: ppvar-sys {
[all …]
/openbmc/u-boot/include/
H A Dcros_ec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
20 struct gpio_desc ec_int; /* GPIO used as EC interrupt line */
25 * These two buffers will always be dword-aligned and include enough
26 * space for up to 7 word-alignment bytes also, so we can ensure that
27 * the body of the message is always dword-aligned (64-bit).
40 * Hard-code the number of columns we happen to know we have right now. It
51 /* Holds information about the Chrome EC */
53 struct fmap_entry flash; /* Address and size of EC flash */
55 * Byte value of erased flash, or -1 if not known. It is normally
63 * Read the ID of the CROS-EC device
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dcros_ec_tunnel.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <i2c.h>
29 return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs); in cros_ec_i2c_xfer()
35 const void *blob = gd->fdt_blob; in cros_ec_i2c_ofdata_to_platdata()
38 i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus", in cros_ec_i2c_ofdata_to_platdata()
50 { .compatible = "google,cros-ec-i2c-tunnel" },
H A Dcros_ec_ldo.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <i2c.h>
29 if (!nmsgs || !msg->len || (msg->flags & I2C_M_RD)) { in cros_ec_ldo_xfer()
34 fet_id = msg->buf[0] - REG_FET_BASE; in cros_ec_ldo_xfer()
43 ret = cros_ec_get_ldo(dev->parent, fet_id, &state); in cros_ec_ldo_xfer()
48 bool on = msg->buf[1] & FET_CTRL_ENFET; in cros_ec_ldo_xfer()
50 ret = cros_ec_set_ldo(dev->parent, fet_id, on); in cros_ec_ldo_xfer()
57 return -ENOSYS; in cros_ec_ldo_xfer()
66 { .compatible = "google,cros-ec-ldo-tunnel" },
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
[all …]
H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
[all …]
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
8 rtc0 = "/i2c@7000d000/pmic@40";
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
41 pll-supply = <&vdd_hdmi_pll>;
[all …]
/openbmc/linux/drivers/platform/chrome/
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
23 * Number of EC preamble bytes we read at a time. Since it takes
24 * about 400-500us for the EC to respond there is not a lot of
25 * point in tuning this. If the EC could respond faster then
34 * Allow for a long time for the EC to respond. We support i2c
35 * tunneling and support fairly long messages for the tunnel (249
43 * not directly passing i2c through, but it's too late for that for
46 * It's pretty unlikely that we'll really see a 249 byte tunnel in
50 * for this, clocking in at 2-3ms.
57 * If we go too fast, the EC will miss the transaction. We know that we
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pit-rev16",
[all …]
H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pi-rev16",
[all …]

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