1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 scp_mem_reserved: memory@50000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x50000000 0 0x2900000>; 114 no-map; 115 }; 116 }; 117 118 sound: mt8183-sound { 119 mediatek,platform = <&afe>; 120 pinctrl-names = "default", 121 "aud_tdm_out_on", 122 "aud_tdm_out_off"; 123 pinctrl-0 = <&aud_pins_default>; 124 pinctrl-1 = <&aud_pins_tdm_out_on>; 125 pinctrl-2 = <&aud_pins_tdm_out_off>; 126 status = "okay"; 127 }; 128 129 btsco: bt-sco { 130 compatible = "linux,bt-sco"; 131 }; 132 133 wifi_pwrseq: wifi-pwrseq { 134 compatible = "mmc-pwrseq-simple"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_pins_pwrseq>; 137 138 /* Toggle WIFI_ENABLE to reset the chip. */ 139 reset-gpios = <&pio 119 1>; 140 }; 141 142 wifi_wakeup: wifi-wakeup { 143 compatible = "gpio-keys"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wifi_pins_wakeup>; 146 147 button-wowlan { 148 label = "Wake on WiFi"; 149 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 150 linux,code = <KEY_WAKEUP>; 151 wakeup-source; 152 }; 153 }; 154 155 tboard_thermistor1: thermal-sensor1 { 156 compatible = "generic-adc-thermal"; 157 #thermal-sensor-cells = <0>; 158 io-channels = <&auxadc 0>; 159 io-channel-names = "sensor-channel"; 160 temperature-lookup-table = < (-5000) 1553 161 0 1488 162 5000 1412 163 10000 1326 164 15000 1232 165 20000 1132 166 25000 1029 167 30000 925 168 35000 823 169 40000 726 170 45000 635 171 50000 552 172 55000 478 173 60000 411 174 65000 353 175 70000 303 176 75000 260 177 80000 222 178 85000 190 179 90000 163 180 95000 140 181 100000 121 182 105000 104 183 110000 90 184 115000 78 185 120000 67 186 125000 59>; 187 }; 188 189 tboard_thermistor2: thermal-sensor2 { 190 compatible = "generic-adc-thermal"; 191 #thermal-sensor-cells = <0>; 192 io-channels = <&auxadc 1>; 193 io-channel-names = "sensor-channel"; 194 temperature-lookup-table = < (-5000) 1553 195 0 1488 196 5000 1412 197 10000 1326 198 15000 1232 199 20000 1132 200 25000 1029 201 30000 925 202 35000 823 203 40000 726 204 45000 635 205 50000 552 206 55000 478 207 60000 411 208 65000 353 209 70000 303 210 75000 260 211 80000 222 212 85000 190 213 90000 163 214 95000 140 215 100000 121 216 105000 104 217 110000 90 218 115000 78 219 120000 67 220 125000 59>; 221 }; 222}; 223 224&auxadc { 225 status = "okay"; 226}; 227 228&cci { 229 proc-supply = <&mt6358_vproc12_reg>; 230}; 231 232&cpu0 { 233 proc-supply = <&mt6358_vproc12_reg>; 234}; 235 236&cpu1 { 237 proc-supply = <&mt6358_vproc12_reg>; 238}; 239 240&cpu2 { 241 proc-supply = <&mt6358_vproc12_reg>; 242}; 243 244&cpu3 { 245 proc-supply = <&mt6358_vproc12_reg>; 246}; 247 248&cpu4 { 249 proc-supply = <&mt6358_vproc11_reg>; 250}; 251 252&cpu5 { 253 proc-supply = <&mt6358_vproc11_reg>; 254}; 255 256&cpu6 { 257 proc-supply = <&mt6358_vproc11_reg>; 258}; 259 260&cpu7 { 261 proc-supply = <&mt6358_vproc11_reg>; 262}; 263 264&dsi0 { 265 status = "okay"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 panel: panel@0 { 269 /* compatible will be set in board dts */ 270 reg = <0>; 271 enable-gpios = <&pio 45 0>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&panel_pins_default>; 274 avdd-supply = <&ppvarn_lcd>; 275 avee-supply = <&ppvarp_lcd>; 276 pp1800-supply = <&pp1800_lcd>; 277 backlight = <&backlight_lcd0>; 278 rotation = <270>; 279 port { 280 panel_in: endpoint { 281 remote-endpoint = <&dsi_out>; 282 }; 283 }; 284 }; 285 286 ports { 287 port { 288 dsi_out: endpoint { 289 remote-endpoint = <&panel_in>; 290 }; 291 }; 292 }; 293}; 294 295&gic { 296 mediatek,broken-save-restore-fw; 297}; 298 299&gpu { 300 mali-supply = <&mt6358_vgpu_reg>; 301}; 302 303&i2c0 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&i2c0_pins>; 306 status = "okay"; 307 clock-frequency = <400000>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310}; 311 312&i2c1 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c1_pins>; 315 status = "okay"; 316 clock-frequency = <100000>; 317}; 318 319&i2c3 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c3_pins>; 322 status = "okay"; 323 clock-frequency = <100000>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326}; 327 328&i2c5 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&i2c5_pins>; 331 status = "okay"; 332 clock-frequency = <100000>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335}; 336 337&i2c6 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&i2c6_pins>; 340 status = "okay"; 341 clock-frequency = <100000>; 342}; 343 344&mipi_tx0 { 345 status = "okay"; 346}; 347 348&mmc0 { 349 status = "okay"; 350 pinctrl-names = "default", "state_uhs"; 351 pinctrl-0 = <&mmc0_pins_default>; 352 pinctrl-1 = <&mmc0_pins_uhs>; 353 bus-width = <8>; 354 max-frequency = <200000000>; 355 cap-mmc-highspeed; 356 mmc-hs200-1_8v; 357 mmc-hs400-1_8v; 358 cap-mmc-hw-reset; 359 no-sdio; 360 no-sd; 361 hs400-ds-delay = <0x12814>; 362 vmmc-supply = <&mt6358_vemc_reg>; 363 vqmmc-supply = <&mt6358_vio18_reg>; 364 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 365 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 366 non-removable; 367}; 368 369&mmc1 { 370 status = "okay"; 371 pinctrl-names = "default", "state_uhs"; 372 pinctrl-0 = <&mmc1_pins_default>; 373 pinctrl-1 = <&mmc1_pins_uhs>; 374 vmmc-supply = <&mmc1_fixed_power>; 375 vqmmc-supply = <&mmc1_fixed_io>; 376 mmc-pwrseq = <&wifi_pwrseq>; 377 bus-width = <4>; 378 max-frequency = <200000000>; 379 cap-sd-highspeed; 380 sd-uhs-sdr50; 381 sd-uhs-sdr104; 382 keep-power-in-suspend; 383 wakeup-source; 384 cap-sdio-irq; 385 non-removable; 386 no-mmc; 387 no-sd; 388 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 389 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 393 qca_wifi: qca-wifi@1 { 394 compatible = "qcom,ath10k"; 395 reg = <1>; 396 }; 397}; 398 399&mt6358_vdram2_reg { 400 regulator-always-on; 401}; 402 403&mt6358codec { 404 Avdd-supply = <&mt6358_vaud28_reg>; 405}; 406 407&mt6358_vgpu_reg { 408 regulator-max-microvolt = <900000>; 409 410 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 411 regulator-coupled-max-spread = <100000>; 412}; 413 414&mt6358_vsim1_reg { 415 regulator-min-microvolt = <2700000>; 416 regulator-max-microvolt = <2700000>; 417}; 418 419&mt6358_vsim2_reg { 420 regulator-min-microvolt = <2700000>; 421 regulator-max-microvolt = <2700000>; 422}; 423 424&mt6358_vsram_gpu_reg { 425 regulator-min-microvolt = <850000>; 426 regulator-max-microvolt = <1000000>; 427 428 regulator-coupled-with = <&mt6358_vgpu_reg>; 429 regulator-coupled-max-spread = <100000>; 430}; 431 432&pio { 433 aud_pins_default: audiopins { 434 pins-bus { 435 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 436 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 437 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 438 <PINMUX_GPIO102__FUNC_I2S2_DI>, 439 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 440 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 441 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 442 <PINMUX_GPIO91__FUNC_I2S5_DO>, 443 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 444 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 445 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 446 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 447 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 448 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 449 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 450 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 451 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 452 }; 453 }; 454 455 aud_pins_tdm_out_on: audiotdmouton { 456 pins-bus { 457 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 458 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 459 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 460 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 461 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 462 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 463 drive-strength = <MTK_DRIVE_6mA>; 464 }; 465 }; 466 467 aud_pins_tdm_out_off: audiotdmoutoff { 468 pins-bus { 469 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 470 <PINMUX_GPIO170__FUNC_GPIO170>, 471 <PINMUX_GPIO171__FUNC_GPIO171>, 472 <PINMUX_GPIO172__FUNC_GPIO172>, 473 <PINMUX_GPIO173__FUNC_GPIO173>, 474 <PINMUX_GPIO10__FUNC_GPIO10>; 475 input-enable; 476 bias-pull-down; 477 drive-strength = <MTK_DRIVE_2mA>; 478 }; 479 }; 480 481 bt_pins: bt-pins { 482 pins-bt-en { 483 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 484 output-low; 485 }; 486 }; 487 488 ec_ap_int_odl: ec-ap-int-odl { 489 pins1 { 490 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 491 input-enable; 492 bias-pull-up; 493 }; 494 }; 495 496 h1_int_od_l: h1-int-od-l { 497 pins1 { 498 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 499 input-enable; 500 }; 501 }; 502 503 i2c0_pins: i2c0 { 504 pins-bus { 505 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 506 <PINMUX_GPIO83__FUNC_SCL0>; 507 mediatek,pull-up-adv = <3>; 508 mediatek,drive-strength-adv = <00>; 509 }; 510 }; 511 512 i2c1_pins: i2c1 { 513 pins-bus { 514 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 515 <PINMUX_GPIO84__FUNC_SCL1>; 516 mediatek,pull-up-adv = <3>; 517 mediatek,drive-strength-adv = <00>; 518 }; 519 }; 520 521 i2c2_pins: i2c2 { 522 pins-bus { 523 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 524 <PINMUX_GPIO104__FUNC_SDA2>; 525 bias-disable; 526 mediatek,drive-strength-adv = <00>; 527 }; 528 }; 529 530 i2c3_pins: i2c3 { 531 pins-bus { 532 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 533 <PINMUX_GPIO51__FUNC_SDA3>; 534 mediatek,pull-up-adv = <3>; 535 mediatek,drive-strength-adv = <00>; 536 }; 537 }; 538 539 i2c4_pins: i2c4 { 540 pins-bus { 541 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 542 <PINMUX_GPIO106__FUNC_SDA4>; 543 bias-disable; 544 mediatek,drive-strength-adv = <00>; 545 }; 546 }; 547 548 i2c5_pins: i2c5 { 549 pins-bus { 550 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 551 <PINMUX_GPIO49__FUNC_SDA5>; 552 mediatek,pull-up-adv = <3>; 553 mediatek,drive-strength-adv = <00>; 554 }; 555 }; 556 557 i2c6_pins: i2c6 { 558 pins-bus { 559 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 560 <PINMUX_GPIO12__FUNC_SDA6>; 561 bias-disable; 562 }; 563 }; 564 565 mmc0_pins_default: mmc0-pins-default { 566 pins-cmd-dat { 567 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 568 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 569 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 570 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 571 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 572 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 573 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 574 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 575 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 576 input-enable; 577 drive-strength = <MTK_DRIVE_14mA>; 578 mediatek,pull-up-adv = <01>; 579 }; 580 581 pins-clk { 582 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 583 drive-strength = <MTK_DRIVE_14mA>; 584 mediatek,pull-down-adv = <10>; 585 }; 586 587 pins-rst { 588 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 589 drive-strength = <MTK_DRIVE_14mA>; 590 mediatek,pull-down-adv = <01>; 591 }; 592 }; 593 594 mmc0_pins_uhs: mmc0-pins-uhs { 595 pins-cmd-dat { 596 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 597 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 598 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 599 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 600 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 601 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 602 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 603 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 604 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 605 input-enable; 606 drive-strength = <MTK_DRIVE_14mA>; 607 mediatek,pull-up-adv = <01>; 608 }; 609 610 pins-clk { 611 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 612 drive-strength = <MTK_DRIVE_14mA>; 613 mediatek,pull-down-adv = <10>; 614 }; 615 616 pins-ds { 617 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 618 drive-strength = <MTK_DRIVE_14mA>; 619 mediatek,pull-down-adv = <10>; 620 }; 621 622 pins-rst { 623 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 624 drive-strength = <MTK_DRIVE_14mA>; 625 mediatek,pull-up-adv = <01>; 626 }; 627 }; 628 629 mmc1_pins_default: mmc1-pins-default { 630 pins-cmd-dat { 631 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 632 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 633 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 634 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 635 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 636 input-enable; 637 mediatek,pull-up-adv = <10>; 638 }; 639 640 pins-clk { 641 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 642 input-enable; 643 mediatek,pull-down-adv = <10>; 644 }; 645 }; 646 647 mmc1_pins_uhs: mmc1-pins-uhs { 648 pins-cmd-dat { 649 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 650 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 651 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 652 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 653 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 654 drive-strength = <MTK_DRIVE_6mA>; 655 input-enable; 656 mediatek,pull-up-adv = <10>; 657 }; 658 659 pins-clk { 660 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 661 drive-strength = <MTK_DRIVE_8mA>; 662 mediatek,pull-down-adv = <10>; 663 input-enable; 664 }; 665 }; 666 667 panel_pins_default: panel-pins-default { 668 panel-reset { 669 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 670 output-low; 671 bias-pull-up; 672 }; 673 }; 674 675 pwm0_pin_default: pwm0-pin-default { 676 pins1 { 677 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 678 output-high; 679 bias-pull-up; 680 }; 681 pins2 { 682 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 683 }; 684 }; 685 686 scp_pins: scp { 687 pins-scp-uart { 688 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 689 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 690 }; 691 }; 692 693 spi0_pins: spi0 { 694 pins-spi { 695 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 696 <PINMUX_GPIO86__FUNC_GPIO86>, 697 <PINMUX_GPIO87__FUNC_SPI0_MO>, 698 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 699 bias-disable; 700 }; 701 }; 702 703 spi1_pins: spi1 { 704 pins-spi { 705 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 706 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 707 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 708 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 709 bias-disable; 710 }; 711 }; 712 713 spi2_pins: spi2 { 714 pins-spi { 715 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 716 <PINMUX_GPIO1__FUNC_SPI2_MO>, 717 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 718 bias-disable; 719 }; 720 pins-spi-mi { 721 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 722 mediatek,pull-down-adv = <00>; 723 }; 724 }; 725 726 spi3_pins: spi3 { 727 pins-spi { 728 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 729 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 730 <PINMUX_GPIO23__FUNC_SPI3_MO>, 731 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 732 bias-disable; 733 }; 734 }; 735 736 spi4_pins: spi4 { 737 pins-spi { 738 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 739 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 740 <PINMUX_GPIO19__FUNC_SPI4_MO>, 741 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 742 bias-disable; 743 }; 744 }; 745 746 spi5_pins: spi5 { 747 pins-spi { 748 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 749 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 750 <PINMUX_GPIO15__FUNC_SPI5_MO>, 751 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 752 bias-disable; 753 }; 754 }; 755 756 uart0_pins_default: uart0-pins-default { 757 pins-rx { 758 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 759 input-enable; 760 bias-pull-up; 761 }; 762 pins-tx { 763 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 764 }; 765 }; 766 767 uart1_pins_default: uart1-pins-default { 768 pins-rx { 769 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 770 input-enable; 771 bias-pull-up; 772 }; 773 pins-tx { 774 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 775 }; 776 pins-rts { 777 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 778 output-enable; 779 }; 780 pins-cts { 781 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 782 input-enable; 783 }; 784 }; 785 786 uart1_pins_sleep: uart1-pins-sleep { 787 pins-rx { 788 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 789 input-enable; 790 bias-pull-up; 791 }; 792 pins-tx { 793 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 794 }; 795 pins-rts { 796 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 797 output-enable; 798 }; 799 pins-cts { 800 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 801 input-enable; 802 }; 803 }; 804 805 wifi_pins_pwrseq: wifi-pins-pwrseq { 806 pins-wifi-enable { 807 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 808 output-low; 809 }; 810 }; 811 812 wifi_pins_wakeup: wifi-pins-wakeup { 813 pins-wifi-wakeup { 814 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 815 input-enable; 816 }; 817 }; 818}; 819 820&pwm0 { 821 status = "okay"; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&pwm0_pin_default>; 824}; 825 826&scp { 827 status = "okay"; 828 829 firmware-name = "mediatek/mt8183/scp.img"; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&scp_pins>; 832 833 cros_ec { 834 compatible = "google,cros-ec-rpmsg"; 835 mediatek,rpmsg-name = "cros-ec-rpmsg"; 836 }; 837}; 838 839&mfg_async { 840 domain-supply = <&mt6358_vsram_gpu_reg>; 841}; 842 843&mfg { 844 domain-supply = <&mt6358_vgpu_reg>; 845}; 846 847&soc_data { 848 status = "okay"; 849}; 850 851&spi0 { 852 pinctrl-names = "default"; 853 pinctrl-0 = <&spi0_pins>; 854 mediatek,pad-select = <0>; 855 status = "okay"; 856 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 857 858 cr50@0 { 859 compatible = "google,cr50"; 860 reg = <0>; 861 spi-max-frequency = <1000000>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&h1_int_od_l>; 864 interrupt-parent = <&pio>; 865 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 866 }; 867}; 868 869&spi1 { 870 pinctrl-names = "default"; 871 pinctrl-0 = <&spi1_pins>; 872 mediatek,pad-select = <0>; 873 status = "okay"; 874 875 w25q64dw: flash@0 { 876 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 877 reg = <0>; 878 spi-max-frequency = <25000000>; 879 }; 880}; 881 882&spi2 { 883 pinctrl-names = "default"; 884 pinctrl-0 = <&spi2_pins>; 885 mediatek,pad-select = <0>; 886 status = "okay"; 887 888 cros_ec: cros-ec@0 { 889 compatible = "google,cros-ec-spi"; 890 reg = <0>; 891 spi-max-frequency = <3000000>; 892 interrupt-parent = <&pio>; 893 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&ec_ap_int_odl>; 896 897 i2c_tunnel: i2c-tunnel { 898 compatible = "google,cros-ec-i2c-tunnel"; 899 google,remote-bus = <1>; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 }; 903 904 usbc_extcon: extcon0 { 905 compatible = "google,extcon-usbc-cros-ec"; 906 google,usb-port-id = <0>; 907 }; 908 909 typec { 910 compatible = "google,cros-ec-typec"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 914 usb_c0: connector@0 { 915 compatible = "usb-c-connector"; 916 reg = <0>; 917 power-role = "dual"; 918 data-role = "host"; 919 try-power-role = "sink"; 920 }; 921 }; 922 }; 923}; 924 925&spi3 { 926 pinctrl-names = "default"; 927 pinctrl-0 = <&spi3_pins>; 928 mediatek,pad-select = <0>; 929 status = "disabled"; 930}; 931 932&spi4 { 933 pinctrl-names = "default"; 934 pinctrl-0 = <&spi4_pins>; 935 mediatek,pad-select = <0>; 936 status = "disabled"; 937}; 938 939&spi5 { 940 pinctrl-names = "default"; 941 pinctrl-0 = <&spi5_pins>; 942 mediatek,pad-select = <0>; 943 status = "disabled"; 944}; 945 946&ssusb { 947 dr_mode = "host"; 948 wakeup-source; 949 vusb33-supply = <&mt6358_vusb_reg>; 950 status = "okay"; 951}; 952 953&thermal_zones { 954 tboard1 { 955 polling-delay = <1000>; /* milliseconds */ 956 polling-delay-passive = <0>; /* milliseconds */ 957 thermal-sensors = <&tboard_thermistor1>; 958 }; 959 960 tboard2 { 961 polling-delay = <1000>; /* milliseconds */ 962 polling-delay-passive = <0>; /* milliseconds */ 963 thermal-sensors = <&tboard_thermistor2>; 964 }; 965}; 966 967&u3phy { 968 status = "okay"; 969}; 970 971&uart0 { 972 pinctrl-names = "default"; 973 pinctrl-0 = <&uart0_pins_default>; 974 status = "okay"; 975}; 976 977&uart1 { 978 pinctrl-names = "default", "sleep"; 979 pinctrl-0 = <&uart1_pins_default>; 980 pinctrl-1 = <&uart1_pins_sleep>; 981 status = "okay"; 982 /delete-property/ interrupts; 983 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 984 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 985 986 bluetooth: bluetooth { 987 pinctrl-names = "default"; 988 pinctrl-0 = <&bt_pins>; 989 status = "okay"; 990 compatible = "qcom,qca6174-bt"; 991 enable-gpios = <&pio 120 0>; 992 clocks = <&clk32k>; 993 firmware-name = "nvm_00440302_i2s.bin"; 994 }; 995}; 996 997&usb_host { 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 vusb33-supply = <&mt6358_vusb_reg>; 1001 status = "okay"; 1002 1003 hub@1 { 1004 compatible = "usb5e3,610"; 1005 reg = <1>; 1006 }; 1007}; 1008 1009#include <arm/cros-ec-sbs.dtsi> 1010