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/openbmc/linux/drivers/irqchip/
H A Dirq-bcm6345-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * ENABLE/STATUS words are packed next to each other for each CPU:
19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
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H A Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
79 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
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H A Dirq-bcm2836.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/cpu.h>
14 #include <linux/irqchip/irq-bcm2836.h>
23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
27 int cpu) in bcm2836_arm_irqchip_mask_per_cpu_irq() argument
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
36 int cpu) in bcm2836_arm_irqchip_unmask_per_cpu_irq() argument
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
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H A Dirq-hip04.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon HiP04 INTC
5 * Copyright (C) 2002-2014 ARM Limited.
6 * Copyright (c) 2013-2014 HiSilicon Ltd.
7 * Copyright (c) 2013-2014 Linaro Ltd.
9 * Interrupt architecture for the HIP04 INTC:
14 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * associated CPU. The base address of the CPU interface is usually
18 * on the CPU it is accessed from.
20 * Note that IRQs 0-31 are special - they are local to each CPU.
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H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
12 #include <linux/cpu.h>
29 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
36 * On RISC-V systems local interrupts are masked or unmasked by writing
44 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
49 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
55 * Andes specific S-mode local interrupt causes (hwirq) in andes_intc_irq_mask()
56 * are defined as (256 + n) and controlled by n-th bit in andes_intc_irq_mask()
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/openbmc/qemu/hw/microblaze/
H A Dxlnx-zynqmp-pmu.c20 #include "exec/address-spaces.h"
22 #include "cpu.h"
25 #include "hw/intc/xlnx-zynqmp-ipi.h"
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc"
54 MicroBlazeCPU cpu; member
55 XlnxPMUIOIntc intc; member
64 object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU); in xlnx_zynqmp_pmu_soc_init()
66 object_initialize_child(obj, "intc", &s->intc, TYPE_XLNX_PMU_IO_INTC); in xlnx_zynqmp_pmu_soc_init()
71 object_initialize_child(obj, name, &s->ipi[i], TYPE_XLNX_ZYNQMP_IPI); in xlnx_zynqmp_pmu_soc_init()
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/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dmicrodev.h1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/include/asm-sh/microdev.h
7 * Definitions for the SuperH SH4-202 MicroDev board.
17 * controller (INTC) on the CPU-board FPGA. should be noted that there
18 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
20 * correctly route - unfortunately, they have the same name and
23 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
24 …INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
25 …NTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-bo…
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/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
42 cpu = <&CPU0>;
45 cpu = <&CPU1>;
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H A Darm-realview-eb.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
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H A Darm-realview-pba8.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
27 model = "ARM RealView Platform Baseboard for Cortex-A8";
28 compatible = "arm,realview-pba8";
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "arm,realview-smp";
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a8";
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/openbmc/qemu/include/hw/ppc/
H A Dspapr_irq.h7 * COPYING file in the top-level directory.
13 #include "target/ppc/cpu-qom.h"
19 * the CPU IPIs are allocated at the bottom of this space, below 4K,
24 * CPU IPI range (XIVE only)
48 #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
58 int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
60 void (*deactivate)(SpaprInterruptController *intc);
66 int (*cpu_intc_create)(SpaprInterruptController *intc,
67 PowerPCCPU *cpu, Error **errp);
68 void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
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/openbmc/linux/arch/arc/boot/dts/
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
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H A Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
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H A Daxc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
7 * Device tree for AXC003 CPU card: HS38x UP configuration
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
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/openbmc/qemu/hw/intc/
H A Dxics_spapr.c44 if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) || in check_emulated_xics()
61 static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr, in h_cppr() argument
68 icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr); in h_cppr()
72 static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr, in h_ipi() argument
88 static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr, in h_xirr() argument
91 uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp); in h_xirr()
99 static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr, in h_xirr_x() argument
102 uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp); in h_xirr_x()
111 static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr, in h_eoi() argument
118 icp_eoi(spapr_cpu_state(cpu)->icp, xirr); in h_eoi()
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/openbmc/qemu/hw/sh4/
H A Dsh7750.c32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
38 #include "exec/exec-all.h"
50 /* CPU */
51 SuperHCPU *cpu; member
80 struct intc_desc intc; member
85 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; in has_bcr3_and_bcr4()
117 return (s->portdira & s->pdtra) | /* CPU */ in porta_lines()
118 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ in porta_lines()
119 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ in porta_lines()
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dqca,ath79-cpu-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
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H A Dqca,ath79-misc-intc.txt7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
23 interrupt-controller@18060010 {
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
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H A Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU.
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
13 peripheral IRQs to be routed to any CPU
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
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/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
16 device_type = "cpu";
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/openbmc/qemu/hw/ppc/
H A Dspapr_irq.c7 * COPYING file in the top-level directory.
12 #include "qemu/error-report.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
36 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { in spapr_irq_msi_init()
41 spapr->irq_map_nr = spapr_irq_nr_msis(spapr); in spapr_irq_msi_init()
42 spapr->irq_map = bitmap_new(spapr->irq_map_nr); in spapr_irq_msi_init()
56 align -= 1; in spapr_irq_msi_alloc()
58 irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num, in spapr_irq_msi_alloc()
60 if (irq == spapr->irq_map_nr) { in spapr_irq_msi_alloc()
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/openbmc/u-boot/arch/x86/dts/
H A Dcherryhill.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <asm/arch-braswell/fsp/fsp_configs.h>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
31 stdout-path = "/serial";
35 #address-cells = <1>;
36 #size-cells = <0>;
38 cpu@0 {
39 device_type = "cpu";
40 compatible = "cpu-x86";
[all …]
H A Dcrownbay.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/interrupt-router/intel-irq.h>
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
36 compatible = "cpu-x86";
38 intel,apic-id = <0>;
41 cpu@1 {
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H A Dbaytrail_som-db5800-som-6867.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
20 model = "Advantech SOM-DB5800-SOM-6867";
21 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
38 pad-offset = <0x220>;
39 mode-func = <2>;
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
22 Node brcm,avs-cpu-data-mem
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