Lines Matching +full:cpu +full:- +full:intc
1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
20 model = "Advantech SOM-DB5800-SOM-6867";
21 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
38 pad-offset = <0x220>;
39 mode-func = <2>;
44 pad-offset = <0x250>;
45 mode-func = <2>;
46 pull-assign = <1>;
51 pad-offset = <0x240>;
52 mode-func = <2>;
57 pad-offset = <0x260>;
58 mode-func = <2>;
59 pull-assign = <1>;
64 pad-offset = <0x270>;
65 mode-func = <2>;
70 pad-offset = <0x560>;
71 mode-func = <1>;
76 stdout-path = "/serial";
80 #address-cells = <1>;
81 #size-cells = <0>;
83 cpu@0 {
84 device_type = "cpu";
85 compatible = "intel,baytrail-cpu";
87 intel,apic-id = <0>;
90 cpu@1 {
91 device_type = "cpu";
92 compatible = "intel,baytrail-cpu";
94 intel,apic-id = <2>;
97 cpu@2 {
98 device_type = "cpu";
99 compatible = "intel,baytrail-cpu";
101 intel,apic-id = <4>;
104 cpu@3 {
105 device_type = "cpu";
106 compatible = "intel,baytrail-cpu";
108 intel,apic-id = <6>;
114 compatible = "intel,pci-baytrail", "pci-x86";
115 #address-cells = <3>;
116 #size-cells = <2>;
117 u-boot,dm-pre-reloc;
125 #address-cells = <1>;
126 #size-cells = <1>;
128 irq-router {
129 compatible = "intel,irq-router";
130 intel,pirq-config = "ibase";
131 intel,ibase-offset = <0x50>;
132 intel,actl-addr = <0>;
133 intel,pirq-link = <8 8>;
134 intel,pirq-mask = <0xdee0>;
135 intel,pirq-routing = <
148 PCI_BDF(0, 24, 1) INTC PIRQC
152 PCI_BDF(0, 24, 5) INTC PIRQC
159 PCI_BDF(0, 28, 2) INTC PIRQC
165 PCI_BDF(0, 30, 3) INTC PIRQC
176 PCI_BDF(1, 0, 0) INTC PIRQC
180 PCI_BDF(2, 0, 0) INTC PIRQD
184 PCI_BDF(3, 0, 0) INTC PIRQA
188 PCI_BDF(4, 0, 0) INTC PIRQB
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "intel,ich9-spi";
197 spi-flash@0 {
198 #address-cells = <1>;
199 #size-cells = <1>;
202 "spi-flash";
203 memory-map = <0xff800000 0x00800000>;
204 rw-mrc-cache {
205 label = "rw-mrc-cache";
212 compatible = "intel,ich6-gpio";
213 u-boot,dm-pre-reloc;
215 bank-name = "A";
216 use-lvl-write-cache;
220 compatible = "intel,ich6-gpio";
221 u-boot,dm-pre-reloc;
223 bank-name = "B";
224 use-lvl-write-cache;
228 compatible = "intel,ich6-gpio";
229 u-boot,dm-pre-reloc;
231 bank-name = "C";
232 use-lvl-write-cache;
236 compatible = "intel,ich6-gpio";
237 u-boot,dm-pre-reloc;
239 bank-name = "D";
240 use-lvl-write-cache;
244 compatible = "intel,ich6-gpio";
245 u-boot,dm-pre-reloc;
247 bank-name = "E";
248 use-lvl-write-cache;
252 compatible = "intel,ich6-gpio";
253 u-boot,dm-pre-reloc;
255 bank-name = "F";
256 use-lvl-write-cache;
262 compatible = "intel,baytrail-fsp";
263 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
264 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
265 fsp,mrc-init-spd-addr1 = <0xa0>;
266 fsp,mrc-init-spd-addr2 = <0xa2>;
267 fsp,enable-spi;
268 fsp,enable-sata;
269 fsp,sata-mode = <SATA_MODE_AHCI>;
270 fsp,enable-azalia;
271 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
272 fsp,enable-dma0;
273 fsp,enable-dma1;
274 fsp,enable-i2c0;
275 fsp,enable-i2c1;
276 fsp,enable-i2c2;
277 fsp,enable-i2c3;
278 fsp,enable-i2c4;
279 fsp,enable-i2c5;
280 fsp,enable-i2c6;
281 fsp,enable-pwm0;
282 fsp,enable-pwm1;
283 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
284 fsp,aperture-size = <APERTURE_SIZE_256MB>;
285 fsp,gtt-size = <GTT_SIZE_2MB>;
286 fsp,scc-mode = <SCC_MODE_PCI>;
287 fsp,os-selection = <OS_SELECTION_LINUX>;
288 fsp,enable-igd;