arc: dts: Harmonize EHCI/OHCI DT nodes name

In accordance with the Generic EHCI/OHCI bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the

arc: dts: Harmonize EHCI/OHCI DT nodes name

In accordance with the Generic EHCI/OHCI bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible
nodes are correctly named.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>

show more ...

ARC: [dts] fix the errors detected by dtbs_check

xxx/arc/boot/dts/axs101.dt.yaml: dw-apb-ictl@e0012000: $nodename:0: \
'dw-apb-ictl@e0012000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
F

ARC: [dts] fix the errors detected by dtbs_check

xxx/arc/boot/dts/axs101.dt.yaml: dw-apb-ictl@e0012000: $nodename:0: \
'dw-apb-ictl@e0012000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
From schema: xxx/interrupt-controller/snps,dw-apb-ictl.yaml

The node name of the interrupt controller must start with
"interrupt-controller" instead of "dw-apb-ictl".

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

ARC: DTB: [scripted] fix node name and address spelling

1. Remove "0x" prefix from unit-address of node names
----------------------->8------------------------
sed -i 's/@0x/@/g' arch/arc/boot/dts/*

ARC: DTB: [scripted] fix node name and address spelling

1. Remove "0x" prefix from unit-address of node names
----------------------->8------------------------
sed -i 's/@0x/@/g' arch/arc/boot/dts/*.dts*
----------------------->8------------------------

2. Make all hex addresses lowercase:
----------------------->8------------------------
sed -i 's/@\([0-9A-Za-z]*\)/@\L\1/g' arch/arc/boot/dts/*.dts*
sed -i 's/0x\([0-9A-Za-z]*\)/0x\L\1/g' arch/arc/boot/dts/*.dts*
----------------------->8------------------------

Inspired by [1] and the like.

[1] http://kisskb.ellerman.id.au/kisskb/buildresult/13612017/

Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: dma [IOC]: mark DMA devices connected as dma-coherent

Mark DMA devices on AXS103 and HSDK boards connected through IOC
port as dma-coherent.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@syn

ARC: dma [IOC]: mark DMA devices connected as dma-coherent

Mark DMA devices on AXS103 and HSDK boards connected through IOC
port as dma-coherent.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be ap

ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.

Update platform quirk for decreasing core frequency for quad core
configuration.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: mm: Decouple RAM base address from kernel link address

[Needed for HSDK]

Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BASE, where kernel itself is

ARC: mm: Decouple RAM base address from kernel link address

[Needed for HSDK]

Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BASE, where kernel itself is linked.

However is case of HSDK platform, for reasons explained in that patch,
this is not true. kernel needs to be linked @ 0x9000_0000 while DDR
is still wired at 0x8000_0000. To properly account for this 256M of RAM,
we need to introduce a new option and base page frame accountiing off of
it.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: renamed CONFIG_KERNEL_RAM_BASE_ADDRESS => CONFIG_LINUX_RAM_BASE
: simplified changelog]

show more ...

ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk

Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signa

ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk

Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [plat-axs10x]: prepare dts files for enabling PAE40 on axs103

Enable 64bit adressing, where it needed, to make possible
enabling PAE40 on axs103.

This patch doesn't affect on any functionality

ARC: [plat-axs10x]: prepare dts files for enabling PAE40 on axs103

Enable 64bit adressing, where it needed, to make possible
enabling PAE40 on axs103.

This patch doesn't affect on any functionality.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARCv2: IDU-intc: Delete deprecated parameters in Device Trees

No need for specifying a list of interrupts in the declaration
of IDU interrupt controller anymore since the kernel can obtain
a number

ARCv2: IDU-intc: Delete deprecated parameters in Device Trees

No need for specifying a list of interrupts in the declaration
of IDU interrupt controller anymore since the kernel can obtain
a number of supported interrupts from the build register.

Also delete support of the second parameter for devices which
are connected to IDU because it is not used anywhere.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

arc: Get rid of root core-frequency property

Now when we switched to usage of real clk devices for CPU core
frequency those root properties make no sense any longer.
Se we're just getting rid of the

arc: Get rid of root core-frequency property

Now when we switched to usage of real clk devices for CPU core
frequency those root properties make no sense any longer.
Se we're just getting rid of them here to not confuse readers of
our .dts files.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Christian Ruppert <christian.ruppert@alitech.com>
Cc: Noam Camus <noamca@mellanox.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core

The most recent release of AXS103 [v1.1] is proven to work
at 100 MHz in dual-core mode so this change uses mentioned feature.
For that we:

arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core

The most recent release of AXS103 [v1.1] is proven to work
at 100 MHz in dual-core mode so this change uses mentioned feature.
For that we:
* Update axc003_idu.dtsi with mention of really-used CPU clock freq
* Remove clock override in AXS platform code for dual-core HW

Note we're still leaving a hack for clock "downgrade" on early boot
for quad-core hardware.

Also note this change will break functionality of AXS103 v1.0 hardware.
That means all users of AXS103 __must__ upgrade their boards with the
most recent firmware.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [dts] Add clk feeding into timers to DTs

This allows us to introduce timers in DT in next commit

The core clk frequency hack in AXS103 platform is also extended,
where the core clk feeding int

ARC: [dts] Add clk feeding into timers to DTs

This allows us to introduce timers in DT in next commit

The core clk frequency hack in AXS103 platform is also extended,
where the core clk feeding into timers is updated in-place in FDT.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [dts] Rename cpu_intc -> core_intc

This is again for future changes to use common DTSI for timers which
refer to @core_intc

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

ARCv2: [dts]: Introduce HS38 specific include DTS ...

... and add them to plat-sim DTS.

This allows for future change to introduce timers in DT in single place

Signed-off-by: Vineet Gupta <vgupta@

ARCv2: [dts]: Introduce HS38 specific include DTS ...

... and add them to plat-sim DTS.

This allows for future change to introduce timers in DT in single place

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [axs10x] Specify reserved memory for frame buffer

Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a

ARC: [axs10x] Specify reserved memory for frame buffer

Allocation of a frame buffer memory in a special memory region
allows bypassing of so-called IO Coherency aperture
which is typically set as a range 0x8z-0xAz.

I.e. all data traffic to PGU bypasses IO Coherency block
and saves its bandwidth for other peripherals.

Even though for AXS101 (which sorts ARC770 CPU) IOC is not
an option for a sake of keeping one DT description for the
base-board (axs10x_mb.dtsi) we're still defining reserved
memory location in the very end of DDR.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com>
Cc: devicetree@vger.kernel.org

show more ...

ARC: Ensure DT mem base is same as what kernel is built with

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ

With up-to-date FPGA builds ARC cores are supposed to correctly operate
even with 90 MHz clock (which is a target frequency for AXS103 release).

ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ

With up-to-date FPGA builds ARC cores are supposed to correctly operate
even with 90 MHz clock (which is a target frequency for AXS103 release).

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: arc-linux-dev@synopsys.com

show more ...

ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gup

ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [dts] fix the errors detected by dtbs_check

xxx/arc/boot/dts/axs101.dt.yaml: dw-apb-ictl@e0012000: $nodename:0: \
'dw-apb-ictl@e0012000' does not match '^interrupt-controller(@[0-9a

ARC: [dts] fix the errors detected by dtbs_check

xxx/arc/boot/dts/axs101.dt.yaml: dw-apb-ictl@e0012000: $nodename:0: \
'dw-apb-ictl@e0012000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
From schema: xxx/interrupt-controller/snps,dw-apb-ictl.yaml

The node name of the interrupt controller must start with
"interrupt-controller" instead of "dw-apb-ictl".

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it u

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

ARC: DTB: [scripted] fix node name and address spelling

1. Remove "0x" prefix from unit-address of node names
----------------------->8------------------------
sed -i 's/@0x/@/g' arc

ARC: DTB: [scripted] fix node name and address spelling

1. Remove "0x" prefix from unit-address of node names
----------------------->8------------------------
sed -i 's/@0x/@/g' arch/arc/boot/dts/*.dts*
----------------------->8------------------------

2. Make all hex addresses lowercase:
----------------------->8------------------------
sed -i 's/@\([0-9A-Za-z]*\)/@\L\1/g' arch/arc/boot/dts/*.dts*
sed -i 's/0x\([0-9A-Za-z]*\)/0x\L\1/g' arch/arc/boot/dts/*.dts*
----------------------->8------------------------

Inspired by [1] and the like.

[1] http://kisskb.ellerman.id.au/kisskb/buildresult/13612017/

Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: dma [IOC]: mark DMA devices connected as dma-coherent

Mark DMA devices on AXS103 and HSDK boards connected through IOC
port as dma-coherent.

Signed-off-by: Eugeniy Paltsev

ARC: dma [IOC]: mark DMA devices connected as dma-coherent

Mark DMA devices on AXS103 and HSDK boards connected through IOC
port as dma-coherent.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.

ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.

Update platform quirk for decreasing core frequency for quad core
configuration.

Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

show more ...

ARC: mm: Decouple RAM base address from kernel link address

[Needed for HSDK]

Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BA

ARC: mm: Decouple RAM base address from kernel link address

[Needed for HSDK]

Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BASE, where kernel itself is linked.

However is case of HSDK platform, for reasons explained in that patch,
this is not true. kernel needs to be linked @ 0x9000_0000 while DDR
is still wired at 0x8000_0000. To properly account for this 256M of RAM,
we need to introduce a new option and base page frame accountiing off of
it.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: renamed CONFIG_KERNEL_RAM_BASE_ADDRESS => CONFIG_LINUX_RAM_BASE
: simplified changelog]

show more ...