| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | mmu.json | 9 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
12 …f a Stage 1 translation table walk handled by the MMU. This event is not counted when it is access…
15 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
18 …f a Stage 2 translation table walk handled by the MMU. This event is not counted when it is access…
|
| H A D | exception.json | 12 …ons and traps caused by HVC instructions are excluded. This event is not counted when it is access…
15 …ons and traps caused by HVC instructions are excluded. This event is not counted when it is access…
|
| /openbmc/linux/tools/lib/perf/include/internal/ |
| H A D | rc_check.h | 24 * counted structs. It leverages address and leak sanitizers to make sure gets
36 /* Declare a reference counted struct variable. */
41 * reference counted struct.
67 /* Declare a reference counted struct variable. */
72 * reference counted struct.
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 21 …n approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fi…
29 …n approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fi…
36 …approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fi…
51 …RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count oth…
60 …RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count oth…
82 …for the top-level metrics of the TMA method. This architectural event is counted on a designated f…
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
|
| H A D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
|
| H A D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
|
| H A D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
|
| H A D | l1d_cache.json | 8 …counted including the multiple accesses caused by single instructions such as LDM or STM. Each acc…
12 … or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidati…
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | bus.json | 4 …rnal bus, including snoop requests and snoop responses. Each beat of data is counted individually."
12 …unts memory read transactions seen on the external bus. Each beat of data is counted individually."
16 …nts memory write transactions seen on the external bus. Each beat of data is counted individually."
|
| H A D | retired.json | 16 …EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers …
20 …whether the branch is taken or not. Instructions that explicitly write to the PC are also counted."
24 …"PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a p…
|
| H A D | l1i_cache.json | 4 …may include accessing multiple instructions, but the single cache line allocation is counted once."
8 …truction cache. Instruction cache accesses caused by cache maintenance operations are not counted."
|
| H A D | l2_cache.json | 12 …ta outside the CPU and snoops which return data from an L1 cache are not counted. Data would not b…
28 …ption": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. …
32 …tion": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. …
|
| H A D | l1d_cache.json | 8 …counted including the multiple accesses caused by single instructions such as LDM or STM. Each acc…
12 … or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidati…
|
| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | others.json | 30 …ption": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this…
90 …e L1 cache was reloaded with a line that fulfills a demand miss request. Counted at reload time, b…
115 "BriefDescription": "Load missed L1, counted at finish time."
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
108 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
171 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
174 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
177 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
180 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
|
| /openbmc/linux/Documentation/userspace-api/media/dvb/ |
| H A D | frontend-stat-properties.rst | 116 - ``FE_SCALE_COUNTER`` - Number of error bits counted before the inner
144 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
173 - ``FE_SCALE_COUNTER`` - Number of error bits counted after the inner
201 - ``FE_SCALE_COUNTER`` - Number of bits counted while measuring
222 - ``FE_SCALE_COUNTER`` - Number of error blocks counted after the outer
244 - ``FE_SCALE_COUNTER`` - Number of blocks counted while measuring
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| H A D | cache.json | 31 … the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
35 …data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted",
62 …data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' tr…
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | virtual-memory.json | 32 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
49 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
58 …. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the n…
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 156 …le walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 trans…
159 …le walk needs to make multiple accesses to the IPA cache, each access is counted. If stage 2 trans…
162 … multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 trans…
165 … multiple accesses to the IPA cache, each access that causes a refill is counted. If stage 2 trans…
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 123 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
126 …refetches cause an allocation. If so, only hardware prefetches should be counted, regardless of wh…
177 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
180 …agewalk needs to make multiple accesses to the IPA cache, each access is counted. +//0 If stage 2 …
183 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
186 …multiple accesses to the IPA cache, each access which causes a refill is counted. +//0 If stage 2 …
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | pipeline.json | 160 …approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fi…
174 …se it is busy processing a previously dispatched uop. The cycles will be counted irrespective of w…
273 …of occurrences a retired load that is a cache line split. Each split should be counted only once.",
296 …f occurrences a retired store that is a cache line split. Each split should be counted only once.",
299 …ced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
|
| /openbmc/linux/tools/perf/tests/shell/ |
| H A D | stat_bpf_counters.sh | 35 echo "Skipping: cycles event not counted"
40 echo "Failed: cycles not counted with --bpf-counters"
|
| H A D | stat+shadow_stat.sh | 19 # skip not counted events
50 # skip not counted events
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 309 …ache long-latency read miss. The counter counts each memory read access counted by L1D_CACHE that…
315 …o-operation architecturally executed. The counter counts each operation counted by OP_SPEC that w…
333 …ation sent for execution on a slot due to the backend. Counts each slot counted by STALL_SLOT whe…
339 …tion sent for execution on a slot due to the frontend. Counts each slot counted by STALL_SLOT whe…
381 …"PublicDescription": "Memory stall cycles. The counter counts each cycle counted by STALL_BACKEND…
387 …counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outsid…
393 …ache long-latency read miss. The counter counts each memory read access counted by L2D_CACHE that…
399 …ache long-latency read miss. The counter counts each memory read access counted by L3D_CACHE that…
|