1[
2    {
3        "BriefDescription": "Loads missed DTLB",
4        "EventCode": "0x04",
5        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
6        "PEBS": "1",
7        "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
8        "SampleAfterValue": "200003",
9        "UMask": "0x8"
10    },
11    {
12        "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
13        "EventCode": "0x05",
14        "EventName": "PAGE_WALKS.CYCLES",
15        "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
16        "SampleAfterValue": "200003",
17        "UMask": "0x3"
18    },
19    {
20        "BriefDescription": "Duration of D-side page-walks in core cycles",
21        "EventCode": "0x05",
22        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
23        "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
24        "SampleAfterValue": "200003",
25        "UMask": "0x1"
26    },
27    {
28        "BriefDescription": "D-side page-walks",
29        "EdgeDetect": "1",
30        "EventCode": "0x05",
31        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
32        "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
33        "SampleAfterValue": "100003",
34        "UMask": "0x1"
35    },
36    {
37        "BriefDescription": "Duration of I-side page-walks in core cycles",
38        "EventCode": "0x05",
39        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
40        "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
41        "SampleAfterValue": "200003",
42        "UMask": "0x2"
43    },
44    {
45        "BriefDescription": "I-side page-walks",
46        "EdgeDetect": "1",
47        "EventCode": "0x05",
48        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
49        "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
50        "SampleAfterValue": "100003",
51        "UMask": "0x2"
52    },
53    {
54        "BriefDescription": "Total page walks that are completed (I-side and D-side)",
55        "EdgeDetect": "1",
56        "EventCode": "0x05",
57        "EventName": "PAGE_WALKS.WALKS",
58        "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
59        "SampleAfterValue": "100003",
60        "UMask": "0x3"
61    }
62]
63