1612a5337SJames Clark[
2612a5337SJames Clark    {
3*44739490SJames Clark        "ArchStdEvent": "BUS_ACCESS",
4*44739490SJames Clark        "PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually."
5612a5337SJames Clark    },
6612a5337SJames Clark    {
7*44739490SJames Clark        "ArchStdEvent": "BUS_CYCLES",
8*44739490SJames Clark        "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES."
9612a5337SJames Clark    },
10612a5337SJames Clark    {
11*44739490SJames Clark        "ArchStdEvent": "BUS_ACCESS_RD",
12*44739490SJames Clark        "PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually."
13612a5337SJames Clark    },
14612a5337SJames Clark    {
15*44739490SJames Clark        "ArchStdEvent": "BUS_ACCESS_WR",
16*44739490SJames Clark        "PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually."
17612a5337SJames Clark    }
18612a5337SJames Clark]
19