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/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A D0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 helgrind/tests/Makefile.am | 6 +++---
18 none/tests/arm/Makefile.am | 18 +++++++++---------
[all …]
H A Duse-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch3 Date: Tue, 19 Jan 2016 16:00:00 -0800
4 Subject: [PATCH] use appropriate -march/-mcpu/-mfpu for ARM test apps
7 -march/-mcpu/-mfpu flags to support the instructions being tested.
12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
14 over-ride that).
18 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
20 Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
21 ---
22 none/tests/arm/Makefile.am | 6 ++++--
[all …]
H A D0001-configure-Drop-setting-mcpu-cortex-a8-on-arm.patch3 Date: Fri, 10 May 2024 16:27:34 -0700
4 Subject: [PATCH] configure: Drop setting mcpu=cortex-a8 on arm
6 The -march settings from environment expresses the flags
10 [1] https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=928224
12 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
13 Signed-off-by: Khem Raj <raj.khem@gmail.com>
14 ---
15 configure.ac | 4 ++--
16 1 file changed, 2 insertions(+), 2 deletions(-)
18 diff --git a/configure.ac b/configure.ac
[all …]
/openbmc/qemu/docs/system/arm/
H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
17 - Arm AMBA Generic/Distributed Interrupt Controller
19 - Four PL011 UARTs
21 - SMC 91c111 or SMSC LAN9118 Ethernet adapter
23 - PL110 LCD controller
25 - PL050 KMI with PS/2 keyboard and mouse
[all …]
H A Dcubieboard.rst5 which is a Cortex-A8 based single-board computer using
10 - Timer
11 - UART
12 - RTC
13 - EMAC
14 - SDHCI
15 - USB controller
16 - SATA controller
17 - TWI (I2C) controller
18 - SPI controller
[all …]
H A Dintegratorcp.rst6 - ARM926E, ARM1026E, ARM946E, ARM1136 or Cortex-A8 CPU
8 - Two PL011 UARTs
10 - SMC 91c111 Ethernet adapter
12 - PL110 LCD controller
14 - PL050 KMI with PS/2 keyboard and mouse.
16 - PL181 MultiMedia Card Interface with SD card.
H A Dversatile.rst6 - ARM926E, ARM1136 or Cortex-A8 CPU
8 - PL190 Vectored Interrupt Controller
10 - Four PL011 UARTs
12 - SMC 91c111 Ethernet adapter
14 - PL110 LCD controller
16 - PL050 KMI with PS/2 keyboard and mouse.
18 - PCI host bridge. Note the emulated PCI bridge only provides access
24 - PCI OHCI USB controller.
26 - LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM
29 - PL181 MultiMedia Card Interface with SD card.
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
92 The AM335x high performance SOC features a Cortex-A8
112 The AM43xx high performance SOC features a Cortex-A9
113 ARM core, a quad core PRU-ICSS for industrial Ethernet
130 The AM335x high performance SOC features a Cortex-A8
131 ARM core, a dual core PRU-ICSS for industrial Ethernet
149 Reserved EMIF region start address. Set to "0" to auto-select
178 boot image. For non-XIP devices, the ROM then copies the image into
181 on the device type (secure/non-secure), boot media (xip/non-xip) and
185 source "arch/arm/mach-omap2/omap3/Kconfig"
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/openbmc/u-boot/doc/
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
16 with -march=armv5 to allow more compilers to work. For U-Boot code this has
48 gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ);
51 gpio_direction_input(&gpio->gpio_a, 0);
54 gpio_direction_output(&gpio->gpio_a, 0, 1);
57 gpio_set_value(&gpio->gpio_a, 0, 0);
60 value = gpio_get_value(&gpio->gpio_a, 0);
H A DREADME.omap35 This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
6 family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
24 * CompuLab Ltd. CM-T35 [8]
59 * CM-T35:
68 To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
81 is typically used to write 2nd stage bootloader (known as 'x-loader') which is
92 ----
121 ---
132 Wait for a transfer to end - this hast to be called before a channel
141 OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page
[all …]
/openbmc/qemu/hw/arm/
H A Dcubieboard.c20 #include "qemu/error-report.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/arm/allwinner-a10.h"
43 if (machine->firmware) { in cubieboard_init()
49 if (machine->ram_size != 512 * MiB && in cubieboard_init()
50 machine->ram_size != 1 * GiB) { in cubieboard_init()
59 if (!object_property_set_int(OBJECT(&a10->emac), "phy-addr", 1, &err)) { in cubieboard_init()
64 if (!object_property_set_int(OBJECT(&a10->timer), "clk0-freq", 32768, in cubieboard_init()
70 if (!object_property_set_int(OBJECT(&a10->timer), "clk1-freq", 24000000, in cubieboard_init()
82 i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c")); in cubieboard_init()
[all …]
H A Drealview.c4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/core/split-irq.h"
20 #include "hw/qdev-core.h"
25 #include "qemu/error-report.h"
33 #include "target/arm/cpu-qom.h"
38 #define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */
66 qdev_prop_set_uint32(splitter, "num-lines", 2); in split_irq_from_named()
93 unsigned int smp_cpus = machine->smp.cpus; in realview_init()
100 ram_addr_t ram_size = machine->ram_size; in realview_init()
121 Object *cpuobj = object_new(machine->cpu_type); in realview_init()
[all …]
H A Dallwinner-a10.c20 #include "qemu/error-report.h"
22 #include "hw/char/serial-mm.h"
24 #include "hw/arm/allwinner-a10.h"
28 #include "hw/usb/hcd-ohci.h"
30 #include "target/arm/cpu-qom.h"
58 rom_add_blob("allwinner-a10.bootrom", buffer, rom_size, in allwinner_a10_bootrom_setup()
67 object_initialize_child(obj, "cpu", &s->cpu, in aw_a10_init()
68 ARM_CPU_TYPE_NAME("cortex-a8")); in aw_a10_init()
70 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC); in aw_a10_init()
72 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); in aw_a10_init()
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa8.inc1 DEFAULTTUNE ?= "cortexa8thf-neon"
3 require conf/machine/include/arm/arch-armv7a.inc
5 TUNEVALID[cortexa8] = "Enable Cortex-A8 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa8', ' -mcpu=cortex-a8', '', d)}"
10 AVAILTUNES += "cortexa8 cortexa8t cortexa8-neon cortexa8t-neon"
11 ARMPKGARCH:tune-cortexa8 = "cortexa8"
12 ARMPKGARCH:tune-cortexa8t = "cortexa8"
13 ARMPKGARCH:tune-cortexa8-neon = "cortexa8"
14 ARMPKGARCH:tune-cortexa8t-neon = "cortexa8"
16 TUNE_FEATURES:tune-cortexa8 = "arm vfp cortexa8"
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/
H A Dvalgrind_3.25.1.bb5 LICENSE = "GPL-2.0-only & GPL-2.0-or-later & BSD-3-Clause"
11 SRC_URI = "https://sourceware.org/pub/valgrind/valgrind-${PV}.tar.bz2 \
12 file://fixed-perl-path.patch \
13 file://Added-support-for-PPC-instructions-mfatbu-mfatbl.patch \
14 file://use-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch \
15 file://avoid-neon-for-targets-which-don-t-support-it.patch \
16 file://0001-configure-Drop-setting-mcpu-cortex-a8-on-arm.patch \
17 file://valgrind-make-ld-XXX.so-strlen-intercept-optional.patch \
18 file://0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch \
19 file://0001-sigqueue-Rename-_sifields-to-__si_fields-on-musl.patch \
[all …]
/openbmc/openbmc/poky/scripts/
H A Dsstate-diff-machines.sh5 # SPDX-License-Identifier: GPL-2.0-only
16 # sstate-diff/1349348392/fake-cortexa8/list.M \
17 # sstate-diff/1349348392/fake-cortexa9/list.M \
18 # | wc -l
22 # $ ls sstate-diff/1349348392/*/armv7a-vfp-neon*/linux-libc-headers/*do_configure*sigdata*
23 # sstate-diff/1349348392/fake-cortexa8/armv7a-vfp-neon-oe-linux-gnueabi/linux-libc-headers/3.4.3-…
24 # sstate-diff/1349348392/fake-cortexa9/armv7a-vfp-neon-oe-linux-gnueabi/linux-libc-headers/3.4.3-…
25 # $ bitbake-diffsigs stamps.1349348392/*/armv7a-vfp-neon*/linux-libc-headers/*do_configure*sigdata*
27 …-march=armv7-a -mthumb-interwork -mfloat-abi=softfp -mfpu=neon -mtune=cortex-a8 to -march=arm…
33 default_machines="qemuarm qemux86 qemux86-64"
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/omap.h>
12 interrupt-parent = <&intc>;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "arm,cortex-a8";
38 compatible = "arm,cortex-a8-pmu";
47 compatible = "ti,omap-infra";
[all …]
H A Domap3.dtsi4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
36 compatible = "arm,cortex-a8";
[all …]
H A Dsun9i-a80-cx-a99.dts2 * sun9i-a80-cx-a99.dts - Device Tree file for the Sunchip CX-A99 board.
6 * This file is dual-licensed: you can use it either under the terms
46 * The Sunchip CX-A99 board is found in several similar Android media
49 * Instabox Fantasy A8 (no external antenna)
50 * Jesurun CS-Q8 (ships with larger remote control)
55 * See the Sunchip CX-A99 page on the Linux-sunxi wiki for more information.
58 /dts-v1/;
59 #include "sun9i-a80.dtsi"
61 #include <dt-bindings/gpio/gpio.h>
64 model = "Sunchip CX-A99";
[all …]
H A Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/am33xx.h>
13 #include <dt-bindings/clock/am3.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 d-can0 = &dcan0;
33 d-can1 = &dcan1;
45 #address-cells = <1>;
[all …]
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
[all …]
/openbmc/openbmc/poky/meta-yocto-bsp/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
18 Note that these reference BSPs use the linux-yocto kernel and in general don't
26 The following boards are supported by the meta-yocto-bsp layer:
28 * Texas Instruments Beaglebone (`beaglebone-yocto`)
29 * General 64-bit Arm SystemReady platforms (`genericarm64`)
30 * General IA platforms (`genericx86` and `genericx86-64`)
38 Please refer to our contributor guide here: https://docs.yoctoproject.org/dev/contributor-guide/
44 git send-email -M -1 --to poky@lists.yoctoproject.org
46 Send pull requests, patches, comments or questions about meta-yocto-bsp to
56 The following consumer devices are supported by the meta-yocto-bsp layer:
[all …]
/openbmc/openbmc/poky/
H A DREADME.hardware.md15 (BSP) Developer's Guide - documentation source is in documentation/bspguide or
18 Note that these reference BSPs use the linux-yocto kernel and in general don't
26 The following boards are supported by the meta-yocto-bsp layer:
28 * Texas Instruments Beaglebone (`beaglebone-yocto`)
29 * General 64-bit Arm SystemReady platforms (`genericarm64`)
30 * General IA platforms (`genericx86` and `genericx86-64`)
38 Please refer to our contributor guide here: https://docs.yoctoproject.org/dev/contributor-guide/
44 git send-email -M -1 --to poky@lists.yoctoproject.org
46 Send pull requests, patches, comments or questions about meta-yocto-bsp to
56 The following consumer devices are supported by the meta-yocto-bsp layer:
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "accel/tcg/cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
26 ARMISARegisters *isar = &cpu->isar; in aa32_max_features()
48 t = cpu->isar.mvfr1; in aa32_max_features()
51 cpu->isar.mvfr1 = t; in aa32_max_features()
53 t = cpu->isar.mvfr2; in aa32_max_features()
56 cpu->isar.mvfr2 = t; in aa32_max_features()
97 cpu->isar.dbgdidr = t; in aa32_max_features()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 adr r0, reset /* r0 <- Runtime value of reset */
50 ldr r1, =reset /* r1 <- Linked value of reset */
51 subs r4, r0, r1 /* r4 <- Run-vs-link offset */
[all …]

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