Lines Matching +full:cortex +full:- +full:a8
2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "accel/tcg/cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
26 ARMISARegisters *isar = &cpu->isar; in aa32_max_features()
48 t = cpu->isar.mvfr1; in aa32_max_features()
51 cpu->isar.mvfr1 = t; in aa32_max_features()
53 t = cpu->isar.mvfr2; in aa32_max_features()
56 cpu->isar.mvfr2 = t; in aa32_max_features()
97 cpu->isar.dbgdidr = t; in aa32_max_features()
108 cpu->isar.dbgdevid = t; in aa32_max_features()
113 cpu->isar.dbgdevid1 = t; in aa32_max_features()
118 /* CPU models. These are not needed for the AArch64 linux-user build. */
125 cpu->dtb_compatible = "arm,arm926"; in arm926_initfn()
126 set_feature(&cpu->env, ARM_FEATURE_V5); in arm926_initfn()
127 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm926_initfn()
128 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); in arm926_initfn()
129 cpu->midr = 0x41069265; in arm926_initfn()
130 cpu->reset_fpsid = 0x41011090; in arm926_initfn()
131 cpu->ctr = 0x1dd20d2; in arm926_initfn()
132 cpu->reset_sctlr = 0x00090078; in arm926_initfn()
138 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); in arm926_initfn()
143 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm926_initfn()
144 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm926_initfn()
145 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); in arm926_initfn()
152 cpu->dtb_compatible = "arm,arm946"; in arm946_initfn()
153 set_feature(&cpu->env, ARM_FEATURE_V5); in arm946_initfn()
154 set_feature(&cpu->env, ARM_FEATURE_PMSA); in arm946_initfn()
155 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm946_initfn()
156 cpu->midr = 0x41059461; in arm946_initfn()
157 cpu->ctr = 0x0f004006; in arm946_initfn()
158 cpu->reset_sctlr = 0x00000078; in arm946_initfn()
165 cpu->dtb_compatible = "arm,arm1026"; in arm1026_initfn()
166 set_feature(&cpu->env, ARM_FEATURE_V5); in arm1026_initfn()
167 set_feature(&cpu->env, ARM_FEATURE_AUXCR); in arm1026_initfn()
168 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1026_initfn()
169 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); in arm1026_initfn()
170 cpu->midr = 0x4106a262; in arm1026_initfn()
171 cpu->reset_fpsid = 0x410110a0; in arm1026_initfn()
172 cpu->ctr = 0x1dd20d2; in arm1026_initfn()
173 cpu->reset_sctlr = 0x00090078; in arm1026_initfn()
174 cpu->reset_auxcr = 1; in arm1026_initfn()
180 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); in arm1026_initfn()
185 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm1026_initfn()
186 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm1026_initfn()
187 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); in arm1026_initfn()
204 ARMISARegisters *isar = &cpu->isar; in arm1136_r2_initfn()
214 cpu->dtb_compatible = "arm,arm1136"; in arm1136_r2_initfn()
215 set_feature(&cpu->env, ARM_FEATURE_V6); in arm1136_r2_initfn()
216 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1136_r2_initfn()
217 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1136_r2_initfn()
218 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1136_r2_initfn()
219 cpu->midr = 0x4107b362; in arm1136_r2_initfn()
220 cpu->reset_fpsid = 0x410120b4; in arm1136_r2_initfn()
221 cpu->isar.mvfr0 = 0x11111111; in arm1136_r2_initfn()
222 cpu->isar.mvfr1 = 0x00000000; in arm1136_r2_initfn()
223 cpu->ctr = 0x1dd20d2; in arm1136_r2_initfn()
224 cpu->reset_sctlr = 0x00050078; in arm1136_r2_initfn()
237 cpu->reset_auxcr = 7; in arm1136_r2_initfn()
243 ARMISARegisters *isar = &cpu->isar; in arm1136_initfn()
245 cpu->dtb_compatible = "arm,arm1136"; in arm1136_initfn()
246 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm1136_initfn()
247 set_feature(&cpu->env, ARM_FEATURE_V6); in arm1136_initfn()
248 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1136_initfn()
249 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1136_initfn()
250 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1136_initfn()
251 cpu->midr = 0x4117b363; in arm1136_initfn()
252 cpu->reset_fpsid = 0x410120b4; in arm1136_initfn()
253 cpu->isar.mvfr0 = 0x11111111; in arm1136_initfn()
254 cpu->isar.mvfr1 = 0x00000000; in arm1136_initfn()
255 cpu->ctr = 0x1dd20d2; in arm1136_initfn()
256 cpu->reset_sctlr = 0x00050078; in arm1136_initfn()
269 cpu->reset_auxcr = 7; in arm1136_initfn()
275 ARMISARegisters *isar = &cpu->isar; in arm1176_initfn()
277 cpu->dtb_compatible = "arm,arm1176"; in arm1176_initfn()
278 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm1176_initfn()
279 set_feature(&cpu->env, ARM_FEATURE_VAPA); in arm1176_initfn()
280 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1176_initfn()
281 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1176_initfn()
282 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1176_initfn()
283 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm1176_initfn()
284 cpu->midr = 0x410fb767; in arm1176_initfn()
285 cpu->reset_fpsid = 0x410120b5; in arm1176_initfn()
286 cpu->isar.mvfr0 = 0x11111111; in arm1176_initfn()
287 cpu->isar.mvfr1 = 0x00000000; in arm1176_initfn()
288 cpu->ctr = 0x1dd20d2; in arm1176_initfn()
289 cpu->reset_sctlr = 0x00050078; in arm1176_initfn()
302 cpu->reset_auxcr = 7; in arm1176_initfn()
308 ARMISARegisters *isar = &cpu->isar; in arm11mpcore_initfn()
310 cpu->dtb_compatible = "arm,arm11mpcore"; in arm11mpcore_initfn()
311 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm11mpcore_initfn()
312 set_feature(&cpu->env, ARM_FEATURE_VAPA); in arm11mpcore_initfn()
313 set_feature(&cpu->env, ARM_FEATURE_MPIDR); in arm11mpcore_initfn()
314 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm11mpcore_initfn()
315 cpu->midr = 0x410fb022; in arm11mpcore_initfn()
316 cpu->reset_fpsid = 0x410120b4; in arm11mpcore_initfn()
317 cpu->isar.mvfr0 = 0x11111111; in arm11mpcore_initfn()
318 cpu->isar.mvfr1 = 0x00000000; in arm11mpcore_initfn()
319 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ in arm11mpcore_initfn()
332 cpu->reset_auxcr = 1; in arm11mpcore_initfn()
345 ARMISARegisters *isar = &cpu->isar; in cortex_a8_initfn()
347 cpu->dtb_compatible = "arm,cortex-a8"; in cortex_a8_initfn()
348 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_a8_initfn()
349 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a8_initfn()
350 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a8_initfn()
351 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a8_initfn()
352 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a8_initfn()
353 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a8_initfn()
354 cpu->midr = 0x410fc080; in cortex_a8_initfn()
355 cpu->reset_fpsid = 0x410330c0; in cortex_a8_initfn()
356 cpu->isar.mvfr0 = 0x11110222; in cortex_a8_initfn()
357 cpu->isar.mvfr1 = 0x00011111; in cortex_a8_initfn()
358 cpu->ctr = 0x82048004; in cortex_a8_initfn()
359 cpu->reset_sctlr = 0x00c50078; in cortex_a8_initfn()
373 cpu->isar.dbgdidr = 0x15141000; in cortex_a8_initfn()
375 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ in cortex_a8_initfn()
376 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ in cortex_a8_initfn()
377 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ in cortex_a8_initfn()
378 cpu->reset_auxcr = 2; in cortex_a8_initfn()
379 cpu->isar.reset_pmcr_el0 = 0x41002000; in cortex_a8_initfn()
415 ARMISARegisters *isar = &cpu->isar; in cortex_a9_initfn()
417 cpu->dtb_compatible = "arm,cortex-a9"; in cortex_a9_initfn()
418 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_a9_initfn()
419 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a9_initfn()
420 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a9_initfn()
421 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a9_initfn()
422 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a9_initfn()
425 * A9UP and single-core A9MP (which are both different in cortex_a9_initfn()
428 set_feature(&cpu->env, ARM_FEATURE_V7MP); in cortex_a9_initfn()
429 set_feature(&cpu->env, ARM_FEATURE_CBAR); in cortex_a9_initfn()
430 cpu->midr = 0x410fc090; in cortex_a9_initfn()
431 cpu->reset_fpsid = 0x41033090; in cortex_a9_initfn()
432 cpu->isar.mvfr0 = 0x11110222; in cortex_a9_initfn()
433 cpu->isar.mvfr1 = 0x01111111; in cortex_a9_initfn()
434 cpu->ctr = 0x80038003; in cortex_a9_initfn()
435 cpu->reset_sctlr = 0x00c50078; in cortex_a9_initfn()
449 cpu->isar.dbgdidr = 0x35141000; in cortex_a9_initfn()
451 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ in cortex_a9_initfn()
452 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ in cortex_a9_initfn()
453 cpu->isar.reset_pmcr_el0 = 0x41093000; in cortex_a9_initfn()
464 * Might as well set the interrupt-controller bit too. in a15_l2ctlr_read()
466 return ((ms->smp.cpus - 1) << 24) | (1 << 23); in a15_l2ctlr_read()
483 ARMISARegisters *isar = &cpu->isar; in cortex_a7_initfn()
485 cpu->dtb_compatible = "arm,cortex-a7"; in cortex_a7_initfn()
486 set_feature(&cpu->env, ARM_FEATURE_V7VE); in cortex_a7_initfn()
487 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a7_initfn()
488 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a7_initfn()
489 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_a7_initfn()
490 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_a7_initfn()
491 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a7_initfn()
492 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_a7_initfn()
493 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_a7_initfn()
494 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a7_initfn()
495 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a7_initfn()
496 cpu->midr = 0x410fc075; in cortex_a7_initfn()
497 cpu->reset_fpsid = 0x41023075; in cortex_a7_initfn()
498 cpu->isar.mvfr0 = 0x10110222; in cortex_a7_initfn()
499 cpu->isar.mvfr1 = 0x11111111; in cortex_a7_initfn()
500 cpu->ctr = 0x84448003; in cortex_a7_initfn()
501 cpu->reset_sctlr = 0x00c50078; in cortex_a7_initfn()
511 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but in cortex_a7_initfn()
512 * table 4-41 gives 0x02101110, which includes the arm div insns. in cortex_a7_initfn()
519 cpu->isar.dbgdidr = 0x3515f005; in cortex_a7_initfn()
520 cpu->isar.dbgdevid = 0x01110f13; in cortex_a7_initfn()
521 cpu->isar.dbgdevid1 = 0x1; in cortex_a7_initfn()
523 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ in cortex_a7_initfn()
524 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ in cortex_a7_initfn()
525 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ in cortex_a7_initfn()
526 cpu->isar.reset_pmcr_el0 = 0x41072000; in cortex_a7_initfn()
533 ARMISARegisters *isar = &cpu->isar; in cortex_a15_initfn()
535 cpu->dtb_compatible = "arm,cortex-a15"; in cortex_a15_initfn()
536 set_feature(&cpu->env, ARM_FEATURE_V7VE); in cortex_a15_initfn()
537 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a15_initfn()
538 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a15_initfn()
539 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_a15_initfn()
540 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_a15_initfn()
541 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a15_initfn()
542 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_a15_initfn()
543 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_a15_initfn()
544 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a15_initfn()
545 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a15_initfn()
547 cpu->midr = 0x414fc0f0; in cortex_a15_initfn()
548 cpu->revidr = 0x0; in cortex_a15_initfn()
549 cpu->reset_fpsid = 0x410430f0; in cortex_a15_initfn()
550 cpu->isar.mvfr0 = 0x10110222; in cortex_a15_initfn()
551 cpu->isar.mvfr1 = 0x11111111; in cortex_a15_initfn()
552 cpu->ctr = 0x8444c004; in cortex_a15_initfn()
553 cpu->reset_sctlr = 0x00c50078; in cortex_a15_initfn()
567 cpu->isar.dbgdidr = 0x3515f021; in cortex_a15_initfn()
568 cpu->isar.dbgdevid = 0x01110f13; in cortex_a15_initfn()
569 cpu->isar.dbgdevid1 = 0x0; in cortex_a15_initfn()
571 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ in cortex_a15_initfn()
572 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ in cortex_a15_initfn()
573 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ in cortex_a15_initfn()
574 cpu->isar.reset_pmcr_el0 = 0x410F3000; in cortex_a15_initfn()
591 ARMISARegisters *isar = &cpu->isar; in cortex_r5_initfn()
593 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_r5_initfn()
594 set_feature(&cpu->env, ARM_FEATURE_V7MP); in cortex_r5_initfn()
595 set_feature(&cpu->env, ARM_FEATURE_PMSA); in cortex_r5_initfn()
596 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_r5_initfn()
597 cpu->midr = 0x411fc153; /* r1p3 */ in cortex_r5_initfn()
613 cpu->mp_is_up = true; in cortex_r5_initfn()
614 cpu->pmsav7_dregion = 16; in cortex_r5_initfn()
615 cpu->isar.reset_pmcr_el0 = 0x41151800; in cortex_r5_initfn()
727 ARMISARegisters *isar = &cpu->isar; in cortex_r52_initfn()
729 set_feature(&cpu->env, ARM_FEATURE_V8); in cortex_r52_initfn()
730 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_r52_initfn()
731 set_feature(&cpu->env, ARM_FEATURE_PMSA); in cortex_r52_initfn()
732 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_r52_initfn()
733 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_r52_initfn()
734 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_r52_initfn()
735 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_r52_initfn()
736 set_feature(&cpu->env, ARM_FEATURE_AUXCR); in cortex_r52_initfn()
737 cpu->midr = 0x411fd133; /* r1p3 */ in cortex_r52_initfn()
738 cpu->revidr = 0x00000000; in cortex_r52_initfn()
739 cpu->reset_fpsid = 0x41034023; in cortex_r52_initfn()
740 cpu->isar.mvfr0 = 0x10110222; in cortex_r52_initfn()
741 cpu->isar.mvfr1 = 0x12111111; in cortex_r52_initfn()
742 cpu->isar.mvfr2 = 0x00000043; in cortex_r52_initfn()
743 cpu->ctr = 0x8144c004; in cortex_r52_initfn()
744 cpu->reset_sctlr = 0x30c50838; in cortex_r52_initfn()
760 cpu->isar.dbgdidr = 0x77168000; in cortex_r52_initfn()
762 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ in cortex_r52_initfn()
763 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ in cortex_r52_initfn()
765 cpu->pmsav7_dregion = 16; in cortex_r52_initfn()
766 cpu->pmsav8r_hdregion = 16; in cortex_r52_initfn()
776 cpu->isar.mvfr0 = 0x10110221; in cortex_r5f_initfn()
777 cpu->isar.mvfr1 = 0x00000011; in cortex_r5f_initfn()
783 set_feature(&cpu->env, ARM_FEATURE_V4T); in ti925t_initfn()
784 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); in ti925t_initfn()
785 cpu->midr = ARM_CPUID_TI925T; in ti925t_initfn()
786 cpu->ctr = 0x5109149; in ti925t_initfn()
787 cpu->reset_sctlr = 0x00000070; in ti925t_initfn()
794 cpu->dtb_compatible = "intel,sa1100"; in sa1100_initfn()
795 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); in sa1100_initfn()
796 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in sa1100_initfn()
797 cpu->midr = 0x4401A11B; in sa1100_initfn()
798 cpu->reset_sctlr = 0x00000070; in sa1100_initfn()
804 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); in sa1110_initfn()
805 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in sa1110_initfn()
806 cpu->midr = 0x6901B119; in sa1110_initfn()
807 cpu->reset_sctlr = 0x00000070; in sa1110_initfn()
814 cpu->dtb_compatible = "marvell,xscale"; in pxa250_initfn()
815 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa250_initfn()
816 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa250_initfn()
817 cpu->midr = 0x69052100; in pxa250_initfn()
818 cpu->ctr = 0xd172172; in pxa250_initfn()
819 cpu->reset_sctlr = 0x00000078; in pxa250_initfn()
826 cpu->dtb_compatible = "marvell,xscale"; in pxa255_initfn()
827 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa255_initfn()
828 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa255_initfn()
829 cpu->midr = 0x69052d00; in pxa255_initfn()
830 cpu->ctr = 0xd172172; in pxa255_initfn()
831 cpu->reset_sctlr = 0x00000078; in pxa255_initfn()
838 cpu->dtb_compatible = "marvell,xscale"; in pxa260_initfn()
839 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa260_initfn()
840 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa260_initfn()
841 cpu->midr = 0x69052903; in pxa260_initfn()
842 cpu->ctr = 0xd172172; in pxa260_initfn()
843 cpu->reset_sctlr = 0x00000078; in pxa260_initfn()
850 cpu->dtb_compatible = "marvell,xscale"; in pxa261_initfn()
851 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa261_initfn()
852 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa261_initfn()
853 cpu->midr = 0x69052d05; in pxa261_initfn()
854 cpu->ctr = 0xd172172; in pxa261_initfn()
855 cpu->reset_sctlr = 0x00000078; in pxa261_initfn()
862 cpu->dtb_compatible = "marvell,xscale"; in pxa262_initfn()
863 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa262_initfn()
864 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa262_initfn()
865 cpu->midr = 0x69052d06; in pxa262_initfn()
866 cpu->ctr = 0xd172172; in pxa262_initfn()
867 cpu->reset_sctlr = 0x00000078; in pxa262_initfn()
874 cpu->dtb_compatible = "marvell,xscale"; in pxa270a0_initfn()
875 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270a0_initfn()
876 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270a0_initfn()
877 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270a0_initfn()
878 cpu->midr = 0x69054110; in pxa270a0_initfn()
879 cpu->ctr = 0xd172172; in pxa270a0_initfn()
880 cpu->reset_sctlr = 0x00000078; in pxa270a0_initfn()
887 cpu->dtb_compatible = "marvell,xscale"; in pxa270a1_initfn()
888 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270a1_initfn()
889 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270a1_initfn()
890 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270a1_initfn()
891 cpu->midr = 0x69054111; in pxa270a1_initfn()
892 cpu->ctr = 0xd172172; in pxa270a1_initfn()
893 cpu->reset_sctlr = 0x00000078; in pxa270a1_initfn()
900 cpu->dtb_compatible = "marvell,xscale"; in pxa270b0_initfn()
901 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270b0_initfn()
902 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270b0_initfn()
903 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270b0_initfn()
904 cpu->midr = 0x69054112; in pxa270b0_initfn()
905 cpu->ctr = 0xd172172; in pxa270b0_initfn()
906 cpu->reset_sctlr = 0x00000078; in pxa270b0_initfn()
913 cpu->dtb_compatible = "marvell,xscale"; in pxa270b1_initfn()
914 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270b1_initfn()
915 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270b1_initfn()
916 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270b1_initfn()
917 cpu->midr = 0x69054113; in pxa270b1_initfn()
918 cpu->ctr = 0xd172172; in pxa270b1_initfn()
919 cpu->reset_sctlr = 0x00000078; in pxa270b1_initfn()
926 cpu->dtb_compatible = "marvell,xscale"; in pxa270c0_initfn()
927 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270c0_initfn()
928 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270c0_initfn()
929 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270c0_initfn()
930 cpu->midr = 0x69054114; in pxa270c0_initfn()
931 cpu->ctr = 0xd172172; in pxa270c0_initfn()
932 cpu->reset_sctlr = 0x00000078; in pxa270c0_initfn()
939 cpu->dtb_compatible = "marvell,xscale"; in pxa270c5_initfn()
940 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270c5_initfn()
941 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270c5_initfn()
942 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270c5_initfn()
943 cpu->midr = 0x69054117; in pxa270c5_initfn()
944 cpu->ctr = 0xd172172; in pxa270c5_initfn()
945 cpu->reset_sctlr = 0x00000078; in pxa270c5_initfn()
950 * -cpu max: a CPU with as many features enabled as our emulation supports.
951 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
957 ARMISARegisters *isar = &cpu->isar; in arm_max_initfn()
960 cpu->dtb_compatible = "arm,cortex-a57"; in arm_max_initfn()
961 set_feature(&cpu->env, ARM_FEATURE_V8); in arm_max_initfn()
962 set_feature(&cpu->env, ARM_FEATURE_NEON); in arm_max_initfn()
963 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in arm_max_initfn()
964 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in arm_max_initfn()
965 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in arm_max_initfn()
966 set_feature(&cpu->env, ARM_FEATURE_EL2); in arm_max_initfn()
967 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm_max_initfn()
968 set_feature(&cpu->env, ARM_FEATURE_PMU); in arm_max_initfn()
969 cpu->midr = 0x411fd070; in arm_max_initfn()
970 cpu->revidr = 0x00000000; in arm_max_initfn()
971 cpu->reset_fpsid = 0x41034070; in arm_max_initfn()
972 cpu->isar.mvfr0 = 0x10110222; in arm_max_initfn()
973 cpu->isar.mvfr1 = 0x12111111; in arm_max_initfn()
974 cpu->isar.mvfr2 = 0x00000043; in arm_max_initfn()
975 cpu->ctr = 0x8444c004; in arm_max_initfn()
976 cpu->reset_sctlr = 0x00c50838; in arm_max_initfn()
992 cpu->isar.reset_pmcr_el0 = 0x41013000; in arm_max_initfn()
994 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ in arm_max_initfn()
995 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ in arm_max_initfn()
996 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ in arm_max_initfn()
1003 * Break with true ARMv8 and add back old-style VFP short-vector support. in arm_max_initfn()
1004 * Only do this for user-mode, where -cpu max is the default, so that in arm_max_initfn()
1007 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm_max_initfn()
1017 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1021 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1025 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1026 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1027 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1028 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1029 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1030 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1031 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1045 /* "pxa270" is an alias for "pxa270-a0" */
1048 { .name = "pxa270-a0", .initfn = pxa270a0_initfn,
1050 { .name = "pxa270-a1", .initfn = pxa270a1_initfn,
1052 { .name = "pxa270-b0", .initfn = pxa270b0_initfn,
1054 { .name = "pxa270-b1", .initfn = pxa270b1_initfn,
1056 { .name = "pxa270-c0", .initfn = pxa270c0_initfn,
1058 { .name = "pxa270-c5", .initfn = pxa270c5_initfn,