cpu/armv7/start.S

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5  * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
10  * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
12  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 	 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 	adr	r0, reset		/* r0 <- Runtime value of reset */
50 	ldr	r1, =reset		/* r1 <- Linked value of reset */
51 	subs	r4, r0, r1		/* r4 <- Run-vs-link offset */
56 	add	r2, r0, r1		/* r2 <- Runtime &__rel_dyn_start */
58 	add	r3, r0, r1		/* r3 <- Runtime &__rel_dyn_start */
61 	ldr	r0, [r2]		/* r0 <- Link location */
62 	ldr	r1, [r2, #4]	/* r1 <- fixup */
108 	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
132 /*------------------------------------------------------------------------------*/
136  * If I-cache is enabled invalidate it
154  * Don't save anything to stack even if compiled with -O0
173  * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
192 	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
193 	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
194 	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
195 	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
197 	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
199 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
252 	bic	r0, r0, #7	/* 8-byte alignment for ABI compliance */
262 	orr	r0, r0, #1 << 7         @ Enable hazard-detect timeout
263 	push	{r1-r5}			@ Save the cpu info registers
266 	pop	{r1-r5}			@ Restore the cpu info - fall through
281 	orr	r0, r0, #3 << 27	@ Disables streaming. All write-allocate
283 	orr	r0, r0, #3 << 25	@ Disables streaming. All write-allocate
285 	push	{r1-r5}			@ Save the cpu info registers
287 	pop	{r1-r5}			@ Restore the cpu info - fall through
294 	push	{r1-r5}			@ Save the cpu info registers
296 	pop	{r1-r5}			@ Restore the cpu info - fall through
305 	push	{r1-r5}			@ Save the cpu info registers
307 	pop	{r1-r5}			@ Restore the cpu info - fall through
319 	push	{r1-r5}			@ Save the cpu info registers
321 	pop	{r1-r5}			@ Restore the cpu info - fall through
330 	push	{r1-r5}			@ Save the cpu info registers
332 	pop	{r1-r5}			@ Restore the cpu info - fall through
338 	cmp	r2, #0x21		@ Only on < r2p1 (Cortex A8)
341 	push	{r1-r5}			@ Save the cpu info registers
343 	pop	{r1-r5}			@ Restore the cpu info - fall through
384 	.word	__rel_dyn_start - pie_fixup
386 	.word	__rel_dyn_end - pie_fixup