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/openbmc/u-boot/arch/arm/dts/
H A Dbcm2836.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
19 arm-pmu {
20 compatible = "arm,cortex-a7-pmu";
21 interrupt-parent = <&local_intc>;
27 compatible = "arm,armv7-timer";
28 interrupt-parent = <&local_intc>;
[all …]
H A Dmt7623.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt7623-clk.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/mt7623-power.h>
13 #include <dt-bindings/reset/mtk-reset.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
47 compatible = "operating-points-v2";
48 opp-shared;
51 opp-hz = /bits/ 64 <648000000>;
52 opp-microvolt = <1040000 1040000 1300000>;
53 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1100000 1100000 1300000>;
59 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
[all …]
H A Dls1021a.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
45 compatible = "arm,armv7-timer";
53 compatible = "arm,cortex-a7-pmu";
[all …]
H A Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-r40-ccu.h>
46 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
H A Dsun8i-v3s.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
44 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
/openbmc/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
41 ---------------
H A Dmcimx6ul-evk.rst1 NXP MCIMX6UL-EVK (``mcimx6ul-evk``)
4 The ``mcimx6ul-evk`` machine models the NXP i.MX6UltraLite Evaluation Kit
5 MCIMX6UL-EVK development board. It has a single Cortex-A7 CPU.
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp528…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz).
15 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
16 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
17 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
22 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
23 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
24 - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
/openbmc/u-boot/arch/arm/mach-mediatek/
H A DKconfig17 The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
18 including NEON and GPU, Mali-450 graphics, several DDR3 options,
19 crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
30 The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
31 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/ne10/ne10/
H A D0001-Dont-specify-march-explicitly.patch3 Date: Wed, 19 Apr 2017 10:11:21 -0700
4 Subject: [PATCH] Dont specify -march explicitly
6 it assumes armv7-a for all armv7 based machines but that may
7 not be true e.g. machines based on armv7ve and cortexa-7
8 it causes conflicts in OE builds because it specifies -march
13 | cc1: warning: switch -mcpu=cortex-a7 conflicts with -march=armv7-a switch
14 | cc1: warning: switch -mcpu=cortex-a7 conflicts with -march=armv7-a switch
16 Signed-off-by: Khem Raj <raj.khem@gmail.com>
17 ---
18 Upstream-Status: Pending
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/qemu/hw/arm/
H A Dorangepi.c22 #include "system/address-spaces.h"
24 #include "qemu/error-report.h"
26 #include "hw/qdev-properties.h"
27 #include "hw/arm/allwinner-h3.h"
41 if (machine->firmware) { in orangepi_init()
47 if (machine->ram_size != 1 * GiB) { in orangepi_init()
57 object_property_set_int(OBJECT(h3), "clk0-freq", 32768, &error_abort); in orangepi_init()
58 object_property_set_int(OBJECT(h3), "clk1-freq", 24 * 1000 * 1000, in orangepi_init()
62 if (qemu_uuid_is_null(&h3->sid.identifier)) { in orangepi_init()
64 "02c00081-1111-2222-3333-000044556677"); in orangepi_init()
[all …]
H A Dbananapi_m2u.c22 #include "system/address-spaces.h"
24 #include "qemu/error-report.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/arm/allwinner-r40.h"
46 bus = qdev_get_child_bus(DEVICE(mmc), "sd-bus"); in mmc_attach_drive()
69 if (machine->firmware) { in bpim2u_init()
79 object_property_set_int(OBJECT(r40), "clk0-freq", 32768, &error_abort); in bpim2u_init()
80 object_property_set_int(OBJECT(r40), "clk1-freq", 24 * 1000 * 1000, in bpim2u_init()
84 r40->ram_size = machine->ram_size / MiB; in bpim2u_init()
85 object_property_set_uint(OBJECT(r40), "ram-addr", in bpim2u_init()
[all …]
H A Dmcimx6ul-evk.c2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
15 #include "hw/arm/fsl-imx6ul.h"
18 #include "hw/qdev-properties.h"
19 #include "qemu/error-report.h"
28 if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) { in mcimx6ul_evk_init()
30 machine->ram_size, FSL_IMX6UL_MMDC_SIZE); in mcimx6ul_evk_init()
36 .board_id = -1, in mcimx6ul_evk_init()
37 .ram_size = machine->ram_size, in mcimx6ul_evk_init()
43 object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal); in mcimx6ul_evk_init()
44 object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal); in mcimx6ul_evk_init()
[all …]
H A Dmcimx7d-sabre.c17 #include "hw/arm/fsl-imx7.h"
20 #include "hw/qdev-properties.h"
21 #include "qemu/error-report.h"
30 if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { in mcimx7d_sabre_init()
32 machine->ram_size, FSL_IMX7_MMDC_SIZE); in mcimx7d_sabre_init()
38 .board_id = -1, in mcimx7d_sabre_init()
39 .ram_size = machine->ram_size, in mcimx7d_sabre_init()
45 object_property_set_bool(OBJECT(s), "fec2-phy-connected", false, in mcimx7d_sabre_init()
50 machine->ram); in mcimx7d_sabre_init()
60 bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); in mcimx7d_sabre_init()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/mach-imx/sys_proto.h>
21 /* Only set the SMP for Cortex A7 */ in enable_ca7_smp()
51 /* Set ACTLR.SMP bit for Cortex-A7 */ in enable_caches()
54 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
69 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are in enable_caches()
70 * disabled by u-boot in enable_caches()
92 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
96 * is cleared, PL310 treats Normal Shared Non-cacheable in v7_outer_cache_enable()
97 * accesses as Cacheable no-allocate. in v7_outer_cache_enable()
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
174 default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa7.inc1 DEFAULTTUNE ?= "cortexa7thf-neon"
3 require conf/machine/include/arm/arch-armv7ve.inc
5 TUNEVALID[cortexa7] = "Enable Cortex-A7 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa7', ' -mcpu=cortex-a7', '', d)}"
10 AVAILTUNES += "cortexa7 cortexa7t cortexa7-neon cortexa7t-neon cortexa7-neon-vfpv4 cortexa7t-neon-v…
11 ARMPKGARCH:tune-cortexa7 = "cortexa7"
12 ARMPKGARCH:tune-cortexa7t = "cortexa7"
13 ARMPKGARCH:tune-cortexa7-neon = "cortexa7"
14 ARMPKGARCH:tune-cortexa7t-neon = "cortexa7"
15 ARMPKGARCH:tune-cortexa7-neon-vfpv4 = "cortexa7"
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/nodejs/nodejs/
H A D0004-v8-don-t-override-ARM-CFLAGS.patch2 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= <git@andred.net>
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This overrides yocto-provided build flags with its own, e.g we get
10 arm-poky-linux-musleabi-g++ -mthumb -mfpu=neon -mfloat-abi=hard -mcpu=cortex-a7 \
12 -march=armv7-a -mfpu=neon -mfloat-abi=hard -marm
15 cc1plus: warning: switch '-mcpu=cortex-a7' conflicts with '-march=armv7-a' switch
17 Patch this out, so that yocto-provided flags take precedence.
24 Upstream-Status: Inappropriate [oe-specific]
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 /* Cortex-A9 revisions */
16 /* Cortex-A15 revisions */
20 /* Cortex-A7 revisions */
/openbmc/qemu/tests/qtest/
H A Darm-cpu-features.c9 * See the COPYING file in the top-level directory.
18 * We expect the SVE max-vq to be 16. Also it must be <= 64
23 #define MACHINE "-machine virt,gic-version=max -accel tcg "
24 #define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
25 #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
191 resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', " in assert_type_full()
207 resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', " in assert_bad_props()
234 if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) && in resp_get_sve_vls()
235 g_ascii_isdigit(e->key[3])) { in resp_get_sve_vls()
239 bits = g_ascii_strtoll(&e->key[3], &endptr, 10); in resp_get_sve_vls()
[all …]

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