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/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A Duse-appropriate-march-mcpu-mfpu-for-ARM-test-apps.patch3 Date: Tue, 19 Jan 2016 16:00:00 -0800
4 Subject: [PATCH] use appropriate -march/-mcpu/-mfpu for ARM test apps
7 -march/-mcpu/-mfpu flags to support the instructions being tested.
12 -march=armv7ve and -mcpu=cortex-a15 (since some TUNE_CCARGS may set
13 -march=armv7-a and adding -mcpu=cortex-a15 alone is not enough to
14 over-ride that).
18 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
20 Signed-off-by: Andre McCurdy <armccurdy@gmail.com>
21 ---
22 none/tests/arm/Makefile.am | 6 ++++--
[all …]
H A D0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 helgrind/tests/Makefile.am | 6 +++---
18 none/tests/arm/Makefile.am | 18 +++++++++---------
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2hk.dtsi2 * Copyright 2013-2014 Texas Instruments, Inc.
13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
31 compatible = "arm,cortex-a15";
37 compatible = "arm,cortex-a15";
44 /include/ "keystone-k2hk-clocks.dtsi"
47 compatible = "ti,keystone-dsp-gpio";
[all …]
H A Dkeystone-k2e.dtsi2 * Copyright 2013-2014 Texas Instruments, Inc.
13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
31 compatible = "arm,cortex-a15";
37 compatible = "arm,cortex-a15";
44 /include/ "keystone-k2e-clocks.dtsi"
54 compatible = "ti,keystone-usbphy";
[all …]
H A Dkeystone-k2l.dtsi13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
32 /include/ "keystone-k2l-clocks.dtsi"
36 current-speed = <115200>;
37 reg-shift = <2>;
38 reg-io-width = <4>;
46 current-speed = <115200>;
[all …]
H A Ddra74x.dtsi2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
18 compatible = "arm,cortex-a15";
20 operating-points-v2 = <&cpu0_opp_table>;
25 compatible = "arm,cortex-a15-pmu";
26 interrupt-parent = <&wakeupgen>;
42 #address-cells = <1>;
43 #size-cells = <1>;
44 utmi-mode = <2>;
53 interrupt-names = "peripheral",
56 maximum-speed = "high-speed";
[all …]
H A Ddra72x.dtsi2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
16 compatible = "arm,cortex-a15-pmu";
17 interrupt-parent = <&wakeupgen>;
26 reg-names = "dss", "pll1_clkctrl", "pll1";
30 clock-names = "fck", "video1_clk";
35 ti,mbox-tx = <6 2 2>;
36 ti,mbox-rx = <4 2 2>;
40 ti,mbox-tx = <5 2 2>;
41 ti,mbox-rx = <1 2 2>;
48 ti,mbox-tx = <6 2 2>;
[all …]
H A Dkeystone-k2g.dtsi11 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&gic>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a15";
46 gic: interrupt-controller {
47 compatible = "arm,cortex-a15-gic";
[all …]
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
[all …]
H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
[all …]
/openbmc/openbmc/poky/meta/conf/machine/
H A Dqemuarm.conf2 #@NAME: QEMU Arm Cortex-A15 machine
5 require conf/machine/include/arm/armv7a/tune-cortexa15.inc
10 PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
16 QB_SYSTEM_NAME = "qemu-system-arm"
17 QB_MACHINE = "-machine virt,highmem=off"
18 QB_CPU = "-cpu cortex-a15"
19 QB_SMP ?= "-smp 4"
21 QB_GRAPHICS = "-device virtio-gpu-pci"
22 QB_OPT_APPEND = "-device qemu-xhci -device usb-tablet -device usb-kbd"
24 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"
[all …]
/openbmc/qemu/tests/functional/
H A Dtest_arm_tuxrun.py12 # SPDX-License-Identifier: GPL-2.0-or-later
26 'https://storage.tuxboot.com/buildroot/20241119/armv5/versatile-pb.dtb',
37 drive="virtio-blk-pci")
48 self.cpu='cortex-a15'
63 self.cpu='cortex-a15'
/openbmc/qemu/docs/system/arm/
H A Dhighbank.rst4 ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5 which has four Cortex-A9 cores.
7 ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8 which has four Cortex-A15 cores.
12 - L2x0 cache controller
13 - SP804 dual timer
14 - PL011 UART
15 - PL061 GPIOs
16 - PL031 RTC
17 - PL022 synchronous serial port controller
[all …]
H A Dvexpress.rst1 Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
7 - ``vexpress-a9`` models the combination of the Versatile Express
9 - ``vexpress-a15`` models the combination of the Versatile Express
17 - PL041 audio
18 - PL181 SD controller
19 - PL050 keyboard and mouse
20 - PL011 UARTs
21 - SP804 timers
22 - I2C controller
23 - PL031 RTC
[all …]
H A Dcpu-features.rst10 Cortex-A15 and the Cortex-A57, which respectively implement Arm
11 architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
12 implement PMUs. For example, if a user wants to use a Cortex-A15 without
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
18 that implement the ARMv8-A architecture reference manual may optionally
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
21 not implement ARMv8-A, will not have the ``aarch64`` CPU property.
30 prefixed with "kvm-" and are described in "KVM VCPU Features".
36 CPU type is possible with the ``query-cpu-model-expansion`` QMP command.
[all …]
H A Dvirt.rst1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - CXL Fixed memory windows, root bridges and devices.
35 - Flash memory
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A DKconfig14 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
33 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
34 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
44 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
45 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
174 default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa15.inc1 DEFAULTTUNE ?= "cortexa15thf-neon"
3 require conf/machine/include/arm/arch-armv7ve.inc
5 TUNEVALID[cortexa15] = "Enable Cortex-A15 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa15', ' -mcpu=cortex-a15', '', d)}"
10 AVAILTUNES += "cortexa15 cortexa15t cortexa15-neon cortexa15t-neon cortexa15-neon-vfpv4 cortexa15t-…
11 ARMPKGARCH:tune-cortexa15 = "cortexa15"
12 ARMPKGARCH:tune-cortexa15t = "cortexa15"
13 ARMPKGARCH:tune-cortexa15-neon = "cortexa15"
14 ARMPKGARCH:tune-cortexa15t-neon = "cortexa15"
15 ARMPKGARCH:tune-cortexa15-neon-vfpv4 = "cortexa15"
[all …]
/openbmc/qemu/tests/qtest/
H A Dmachine-none-test.c10 * See the COPYING file in the top-level directory.
27 { "arm", "cortex-a15" },
28 { "aarch64", "cortex-a57" },
29 { "avr", "avr6-avr-cpu" },
30 { "x86_64", "qemu64,apic-id=0" },
31 { "i386", "qemu32,apic-id=0" },
82 qts = qtest_initf("-machine none -cpu \"%s\"", cpu_model); in test_machine_cpu_cli()
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 /* Cortex-A9 revisions */
16 /* Cortex-A15 revisions */
20 /* Cortex-A7 revisions */
/openbmc/openbmc/poky/meta-yocto-bsp/conf/machine/
H A Dbeaglebone-yocto.conf2 #@NAME: Beaglebone-yocto machine
5 PREFERRED_PROVIDER_virtual/xserver ?= "xserver-xorg"
7 MACHINE_EXTRA_RRECOMMENDS = "kernel-modules"
11 DEFAULTTUNE ?= "cortexa8hf-neon"
12 include conf/machine/include/arm/armv7a/tune-cortexa8.inc
15 EXTRA_IMAGECMD:jffs2 = "-lnp "
16 WKS_FILE ?= "beaglebone-yocto.wks"
17 MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image kernel-devicetree"
18 do_image_wic[depends] += "mtools-native:do_populate_sysroot dosfstools-native:do_populate_sysroot v…
22 PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
[all …]
/openbmc/qemu/hw/arm/
H A Dvexpress.c4 * Copyright (c) 2010 - 2011 B Labs Ltd.
20 * Contributions after 2012-01-13 are licensed under the terms of the
38 #include "qemu/error-report.h"
48 #include "target/arm/cpu-qom.h"
63 * the "legacy" one (used for A9) and the "Cortex-A Series"
189 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
190 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
218 unsigned int smp_cpus = ms->smp.cpus; in init_cpus()
233 if (object_property_find(cpuobj, "reset-cbar")) { in init_cpus()
234 object_property_set_int(cpuobj, "reset-cbar", periphbase, in init_cpus()
[all …]
H A Dhighbank.c4 * Copyright (c) 2010-2012 Calxeda
31 #include "qemu/error-report.h"
33 #include "hw/ide/ahci-sysbus.h"
39 #include "target/arm/cpu-qom.h"
48 #define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */
100 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
113 .name = "highbank-regs",
126 s->regs[0x40] = 0x05F20121; in highbank_regs_reset()
127 s->regs[0x41] = 0x2; in highbank_regs_reset()
128 s->regs[0x42] = 0x05F30121; in highbank_regs_reset()
[all …]
/openbmc/openbmc/poky/meta/recipes-extended/baremetal-example/
H A Dbaremetal-helloworld_git.bb2 HOMEPAGE = "https://github.com/aehs29/baremetal-helloqemu"
10 SRC_URI = "git://github.com/ahcbb6/baremetal-helloqemu.git;protocol=https;branch=master"
17 IMAGE_LINK_NAME ?= "baremetal-helloworld-image-${MACHINE}"
20 # Baremetal-Image creates the proper wiring, assumes the output is provided in
24 inherit baremetal-image
28 DEPENDS:qemux86:append = " nasm-native"
32 # machine that QEMU uses on OE, e.g. -machine virt -cpu cortex-a57
34 # such as vexpress-a15 by overriding the setting on the machine.conf
35 COMPATIBLE_MACHINE = "qemuarmv5|qemuarm|qemuarm64|qemuriscv64|qemuriscv32|qemux86|qemux86-64"
44 BAREMETAL_QEMUARCH:qemux86-64 = "x86-64"
[all …]

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