1e5520e18SMugunthan V N/* 2e5520e18SMugunthan V N * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3e5520e18SMugunthan V N * 4e5520e18SMugunthan V N * This program is free software; you can redistribute it and/or modify 5e5520e18SMugunthan V N * it under the terms of the GNU General Public License version 2 as 6e5520e18SMugunthan V N * published by the Free Software Foundation. 7e5520e18SMugunthan V N * Based on "omap4.dtsi" 8e5520e18SMugunthan V N */ 9e5520e18SMugunthan V N 10e5520e18SMugunthan V N#include "dra7.dtsi" 11e5520e18SMugunthan V N 12e5520e18SMugunthan V N/ { 13e5520e18SMugunthan V N compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14e5520e18SMugunthan V N 15e5520e18SMugunthan V N cpus { 16e5520e18SMugunthan V N cpu@1 { 17e5520e18SMugunthan V N device_type = "cpu"; 18e5520e18SMugunthan V N compatible = "arm,cortex-a15"; 19e5520e18SMugunthan V N reg = <1>; 20*4ddaa6ceSLokesh Vutla operating-points-v2 = <&cpu0_opp_table>; 21e5520e18SMugunthan V N }; 22e5520e18SMugunthan V N }; 23e5520e18SMugunthan V N 24e5520e18SMugunthan V N pmu { 25e5520e18SMugunthan V N compatible = "arm,cortex-a15-pmu"; 26e5520e18SMugunthan V N interrupt-parent = <&wakeupgen>; 27e5520e18SMugunthan V N interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 28e5520e18SMugunthan V N <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 29e5520e18SMugunthan V N }; 30e5520e18SMugunthan V N 31e5520e18SMugunthan V N ocp { 32*4ddaa6ceSLokesh Vutla dsp2_system: dsp_system@41500000 { 33*4ddaa6ceSLokesh Vutla compatible = "syscon"; 34*4ddaa6ceSLokesh Vutla reg = <0x41500000 0x100>; 35*4ddaa6ceSLokesh Vutla }; 36*4ddaa6ceSLokesh Vutla 37e5520e18SMugunthan V N omap_dwc3_4: omap_dwc3_4@48940000 { 38e5520e18SMugunthan V N compatible = "ti,dwc3"; 39e5520e18SMugunthan V N ti,hwmods = "usb_otg_ss4"; 40e5520e18SMugunthan V N reg = <0x48940000 0x10000>; 41e5520e18SMugunthan V N interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 42e5520e18SMugunthan V N #address-cells = <1>; 43e5520e18SMugunthan V N #size-cells = <1>; 44e5520e18SMugunthan V N utmi-mode = <2>; 45e5520e18SMugunthan V N ranges; 46e5520e18SMugunthan V N status = "disabled"; 47e5520e18SMugunthan V N usb4: usb@48950000 { 48e5520e18SMugunthan V N compatible = "snps,dwc3"; 49e5520e18SMugunthan V N reg = <0x48950000 0x17000>; 50*4ddaa6ceSLokesh Vutla interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 51*4ddaa6ceSLokesh Vutla <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 52*4ddaa6ceSLokesh Vutla <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 53*4ddaa6ceSLokesh Vutla interrupt-names = "peripheral", 54*4ddaa6ceSLokesh Vutla "host", 55*4ddaa6ceSLokesh Vutla "otg"; 56e5520e18SMugunthan V N maximum-speed = "high-speed"; 57e5520e18SMugunthan V N dr_mode = "otg"; 58e5520e18SMugunthan V N }; 59e5520e18SMugunthan V N }; 60*4ddaa6ceSLokesh Vutla 61*4ddaa6ceSLokesh Vutla mmu0_dsp2: mmu@41501000 { 62*4ddaa6ceSLokesh Vutla compatible = "ti,dra7-dsp-iommu"; 63*4ddaa6ceSLokesh Vutla reg = <0x41501000 0x100>; 64*4ddaa6ceSLokesh Vutla interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 65*4ddaa6ceSLokesh Vutla ti,hwmods = "mmu0_dsp2"; 66*4ddaa6ceSLokesh Vutla #iommu-cells = <0>; 67*4ddaa6ceSLokesh Vutla ti,syscon-mmuconfig = <&dsp2_system 0x0>; 68*4ddaa6ceSLokesh Vutla status = "disabled"; 69e5520e18SMugunthan V N }; 70*4ddaa6ceSLokesh Vutla 71*4ddaa6ceSLokesh Vutla mmu1_dsp2: mmu@41502000 { 72*4ddaa6ceSLokesh Vutla compatible = "ti,dra7-dsp-iommu"; 73*4ddaa6ceSLokesh Vutla reg = <0x41502000 0x100>; 74*4ddaa6ceSLokesh Vutla interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 75*4ddaa6ceSLokesh Vutla ti,hwmods = "mmu1_dsp2"; 76*4ddaa6ceSLokesh Vutla #iommu-cells = <0>; 77*4ddaa6ceSLokesh Vutla ti,syscon-mmuconfig = <&dsp2_system 0x1>; 78*4ddaa6ceSLokesh Vutla status = "disabled"; 79*4ddaa6ceSLokesh Vutla }; 80*4ddaa6ceSLokesh Vutla }; 81*4ddaa6ceSLokesh Vutla}; 82*4ddaa6ceSLokesh Vutla 83*4ddaa6ceSLokesh Vutla&cpu0_opp_table { 84*4ddaa6ceSLokesh Vutla opp-shared; 85e5520e18SMugunthan V N}; 86e5520e18SMugunthan V N 87e5520e18SMugunthan V N&dss { 88e5520e18SMugunthan V N reg = <0x58000000 0x80>, 89e5520e18SMugunthan V N <0x58004054 0x4>, 90e5520e18SMugunthan V N <0x58004300 0x20>, 91*4ddaa6ceSLokesh Vutla <0x58009054 0x4>, 92*4ddaa6ceSLokesh Vutla <0x58009300 0x20>; 93e5520e18SMugunthan V N reg-names = "dss", "pll1_clkctrl", "pll1", 94e5520e18SMugunthan V N "pll2_clkctrl", "pll2"; 95e5520e18SMugunthan V N 96e5520e18SMugunthan V N clocks = <&dss_dss_clk>, 97e5520e18SMugunthan V N <&dss_video1_clk>, 98e5520e18SMugunthan V N <&dss_video2_clk>; 99e5520e18SMugunthan V N clock-names = "fck", "video1_clk", "video2_clk"; 100e5520e18SMugunthan V N}; 101*4ddaa6ceSLokesh Vutla 102*4ddaa6ceSLokesh Vutla&mailbox5 { 103*4ddaa6ceSLokesh Vutla mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 104*4ddaa6ceSLokesh Vutla ti,mbox-tx = <6 2 2>; 105*4ddaa6ceSLokesh Vutla ti,mbox-rx = <4 2 2>; 106*4ddaa6ceSLokesh Vutla status = "disabled"; 107*4ddaa6ceSLokesh Vutla }; 108*4ddaa6ceSLokesh Vutla mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 109*4ddaa6ceSLokesh Vutla ti,mbox-tx = <5 2 2>; 110*4ddaa6ceSLokesh Vutla ti,mbox-rx = <1 2 2>; 111*4ddaa6ceSLokesh Vutla status = "disabled"; 112*4ddaa6ceSLokesh Vutla }; 113*4ddaa6ceSLokesh Vutla}; 114*4ddaa6ceSLokesh Vutla 115*4ddaa6ceSLokesh Vutla&mailbox6 { 116*4ddaa6ceSLokesh Vutla mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 117*4ddaa6ceSLokesh Vutla ti,mbox-tx = <6 2 2>; 118*4ddaa6ceSLokesh Vutla ti,mbox-rx = <4 2 2>; 119*4ddaa6ceSLokesh Vutla status = "disabled"; 120*4ddaa6ceSLokesh Vutla }; 121*4ddaa6ceSLokesh Vutla mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { 122*4ddaa6ceSLokesh Vutla ti,mbox-tx = <5 2 2>; 123*4ddaa6ceSLokesh Vutla ti,mbox-rx = <1 2 2>; 124*4ddaa6ceSLokesh Vutla status = "disabled"; 125*4ddaa6ceSLokesh Vutla }; 126*4ddaa6ceSLokesh Vutla}; 127