system/arm/virt.rst

1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - CXL Fixed memory windows, root bridges and devices.
35 - Flash memory
36 - Either one or two PL011 UARTs for the NonSecure World
37 - An RTC
38 - The fw_cfg device that allows a guest to obtain data from QEMU
39 - A PL061 GPIO controller
40 - An optional SMMUv3 IOMMU
41 - hotpluggable DIMMs
42 - hotpluggable NVDIMMs
43 - An MSI controller (GICv2M or ITS). GICv2M is selected by default along
44   with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
46 - 32 virtio-mmio transport devices
47 - running guests using the KVM accelerator on aarch64 hardware
48 - large amounts of RAM (at least 255GB, and more if using highmem)
49 - many CPUs (up to 512 if using a GICv3 and highmem)
50 - Secure-World-only devices if the CPU has TrustZone:
52   - A second PL011 UART
53   - A second PL061 GPIO controller, with GPIO lines for triggering
55   - A secure flash memory
56   - 16MB of secure RAM
59 explicitly (e.g. with a second -serial command line option) and
64 - ``cortex-a7`` (32-bit)
65 - ``cortex-a15`` (32-bit; the default)
66 - ``cortex-a35`` (64-bit)
67 - ``cortex-a53`` (64-bit)
68 - ``cortex-a55`` (64-bit)
69 - ``cortex-a57`` (64-bit)
70 - ``cortex-a72`` (64-bit)
71 - ``cortex-a76`` (64-bit)
72 - ``cortex-a710`` (64-bit)
73 - ``a64fx`` (64-bit)
74 - ``host`` (with KVM and HVF only)
75 - ``neoverse-n1`` (64-bit)
76 - ``neoverse-v1`` (64-bit)
77 - ``neoverse-n2`` (64-bit)
78 - ``max`` (same as ``host`` for KVM and HVF; best possible emulation with TCG)
80 Note that the default is ``cortex-a15``, so for an AArch64 guest you must
83 Also, please note that passing ``max`` CPU (i.e. ``-cpu max``) won't
89 For example, MTE support must be enabled with ``-machine virt,mte=on``,
90 as well as by selecting an MTE-capable CPU (e.g., ``max``) with the
91 ``-cpu`` option.
93 See the machine-specific options below, or check them for a given machine
94 by passing the ``help`` suboption, like: ``-machine virt-9.0,help``.
98 the Display devices section of "-device help". The recommended option
99 is ``virtio-gpu-pci``; this is the only one which will work correctly
103 Machine-specific options
106 The following machine-specific options are supported:
123   later than ``virt-2.12`` when the CPU supports an address space
124   bigger than 32 bits (i.e. 64-bit CPUs, and 32-bit CPUs with the
126   boot a 32-bit kernel which does not have ``CONFIG_LPAE`` enabled on
131 compact-highmem
133   The default is ``on`` for machine types later than ``virt-7.2``.
135 highmem-redists
140 highmem-ecam
142   The default is ``on`` for machine types later than ``virt-3.0``.
144 highmem-mmio
148 highmem-mmio-size
152 gic-version
171   for machine types later than ``virt-2.7``.
181 default-bus-bypass-iommu
183   <https://gitlab.com/qemu-project/qemu/-/blob/master/docs/bypass-iommu.txt>`_
197 cxl-fmw
201 dtb-randomness
203   rng-seed and kaslr-seed nodes (in both "/chosen" and
204   "/secure-chosen") to use for features like the random number
208   DTB to be non-deterministic. It would be the responsibility of
211 dtb-kaslr-seed
212   A deprecated synonym for dtb-randomness.
214 x-oem-id
218 x-oem-table-id
227 kernel versions, especially for 32-bit Arm, did not have everything
235 If you want to use the ``virtio-gpu-pci`` graphics device you will also
241 Hardware configuration information for bare-metal programming
247 in the system. Guest code can rely on and hard-code the following
250 - Flash memory starts at address 0x0000_0000
252 - RAM starts at 0x4000_0000
260 - For guests using the Linux kernel boot protocol (this means any
261   non-ELF file passed to the QEMU ``-kernel`` option) the address
262   of the DTB is passed in a register (``r2`` for 32-bit guests,
263   or ``x0`` for 64-bit guests)
265 - For guests booting as "bare-metal" (any other kind of boot),