Home
last modified time | relevance | path

Searched +full:coresight +full:- +full:stm (Results 1 – 25 of 41) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight System Trace MacroCell
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
[all …]
/openbmc/linux/Documentation/trace/coresight/
H A Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
[all …]
H A Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-stm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 * Description: CoreSight System Trace Macrocell driver
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
23 #include <linux/coresight.h>
24 #include <linux/coresight-stm.h>
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
5 obj-$(CONFIG_CORESIGHT) += coresight.o
6 coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
7 coresight-sysfs.o coresight-syscfg.o coresight-config.o \
8 coresight-cfg-preload.o coresight-cfg-afdo.o \
9 coresight-syscfg-configfs.o coresight-trace-id.o
10 obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
11 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
12 coresight-tmc-etr.o
[all …]
H A Dcoresight-trace-id.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Coresight trace ID allocation API
20 * throughout a perf cs_etm event session - a session in progress flag will
22 * complete. This allows the same CPU to be re-allocated its prior ID.
28 * API permits multiple maps to be maintained - for large systems where
56 * yet marked as available, to allow re-allocation to the same
67 * Read and optionally allocate a CoreSight trace ID and associate with a CPU.
77 * return: CoreSight trace ID or -EINVAL if allocation impossible.
84 * This will release the CoreSight trace ID associated with the CPU,
95 * Read the current allocated CoreSight Trace ID value for the CPU.
[all …]
/openbmc/linux/drivers/hwtracing/stm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 config STM config
6 A System Trace Module (STM) is a device exporting data in System
8 Examples of such devices are Intel(R) Trace Hub and Coresight STM.
12 if STM
15 tristate "Basic STM framing protocol driver"
18 This is a simple framing protocol for sending data over STM
19 devices. This was the protocol that the STM framework used
20 exclusively until the MIPI SyS-T support was added. Use this
21 driver for compatibility with your existing STM setup.
[all …]
/openbmc/linux/include/uapi/linux/
H A Dcoresight-stm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 * The CoreSight STM supports guaranteed and invariant timing
15 * ensure the transaction is accepted by the STM. While invariant
18 * state of the STM.
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
[all …]
/openbmc/linux/drivers/acpi/arm64/
H A Damba.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
24 {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */
25 {"ARMHC501", 0}, /* ARM CoreSight ETR */
26 {"ARMHC502", 0}, /* ARM CoreSight STM */
27 {"ARMHC503", 0}, /* ARM CoreSight Debug */
28 {"ARMHC979", 0}, /* ARM CoreSight TPIU */
29 {"ARMHC97C", 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
30 {"ARMHC98D", 0}, /* ARM CoreSight Dynamic Replicator */
31 {"ARMHC9CA", 0}, /* ARM CoreSight CATU */
[all …]
/openbmc/linux/Documentation/trace/
H A Dstm.rst1 .. SPDX-License-Identifier: GPL-2.0
7 System Trace Module (STM) is a device described in MIPI STP specs as
26 To solve this mapping problem, stm class provides a policy management
34 associated with it, located in "stp-policy" subsystem directory in
36 the STM device name to which this policy applies and an arbitrary
40 $ ls /config/stp-policy/dummy_stm.my-policy/user
42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
44 $ cat /config/stp-policy/dummy_stm.my-policy/user/channels
57 Trace sources have to open the stm class device's node and write their
67 stm core will try to find a policy node with the name matching the
[all …]
H A Dindex.rst8 ftrace-design
9 tracepoint-analysis
11 ftrace-uses
19 events-kmem
20 events-power
21 events-nmi
22 events-msr
25 histogram-design
26 boottime-trace
28 osnoise-tracer
[all …]
/openbmc/linux/include/linux/
H A Dcoresight-stm.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <uapi/linux/coresight-stm.h>
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
[all …]
H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
H A Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
[all …]
H A Dsm8150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
[all …]
/openbmc/linux/drivers/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Rewritten to use lists instead of if-statements.
11 MAKEFLAGS += --include-dir=$(srctree)
14 obj-y += cache/
15 obj-y += irqchip/
16 obj-y += bus/
18 obj-$(CONFIG_GENERIC_PHY) += phy/
21 obj-$(CONFIG_PINCTRL) += pinctrl/
22 obj-$(CONFIG_GPIOLIB) += gpio/
23 obj-y += pwm/
[all …]
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
205 if (hdev->pldm) in goya_coresight_timeout()
219 dev_err(hdev->dev, in goya_coresight_timeout()
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
222 return -EFAULT; in goya_coresight_timeout()
236 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
237 dev_err(hdev->dev, "Invalid register index in STM\n"); in goya_config_stm()
238 return -EINVAL; in goya_config_stm()
241 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
[all …]
/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2019-2022 HabanaLabs, Ltd.
13 #define COMPONENT_ID_INVALID ((u32)(-1))
45 * struct component_config_offsets - per cs_dbg unit - view off all related components indices
46 * @funnel_id: funnel id - index in debug_funnel_regs
47 * @etf_id: etf id - index in debug_etf_regs
48 * @stm_id: stm id - index in debug_stm_regs
49 * @spmu_id: spmu_id - index in debug_spmu_regs
51 * @bmon_ids: array of bmon id (max size - MAX_BMONS_PER_UNIT) index in debug_bmon_regs
1933 if (hdev->pldm) in gaudi2_coresight_timeout()
[all …]
H A Dgaudi2_coresight_regs.h1 /* SPDX-License-Identifier: GPL-2.0
14 /* FUNNEL Offsets - same offsets for all funnels*/
16 (mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG - \
20 (mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG - \
24 (mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 - \
28 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 - \
32 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 - \
36 (mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 - \
40 (mmDCORE0_TPC0_EML_FUNNEL_ITCTRL - \
44 (mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET - \
[all …]

12