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Searched +full:cmdq +full:- +full:sync (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_reqmgr.c1 // SPDX-License-Identifier: GPL-2.0
24 * 0x00 - Success
26 * 0x43 - ERR_GC_DATA_LEN_INVALID
28 * less than 16 bytes for AES-XTS and AES-CTS.
29 * 0x45 - ERR_GC_CTX_LEN_INVALID
31 * 0x4F - ERR_GC_DOCSIS_CIPHER_INVALID
33 * AES/DES-CBC mode encryption.
34 * 0x50 - ERR_GC_DOCSIS_OFFSET_INVALID
39 * 0x51 - ERR_GC_CRC32_INVALID_SELECTION
41 * 0x52 - ERR_GC_AES_CCM_FLAG_INVALID
[all …]
/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
30 #include "arm-smmu-v3.h"
31 #include "../../dma-iommu.h"
32 #include "../../iommu-sva.h"
42 "Disable MSI-based polling for CMD_SYNC completion.");
84 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
85 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
94 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
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H A Darm-smmu-v3.h1 /* SPDX-License-Identifier: GPL-2.0-only */
94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
175 #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
176 #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
179 #define Q_ENT(q, p) ((q)->base + \
180 Q_IDX(&((q)->llq), p) * \
181 (q)->ent_dwords)
312 #define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
382 #define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
408 #define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/openbmc/linux/include/dt-bindings/gce/
H A Dmt8186-gce.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
82 /* CMDQ: debug */
85 /* CMDQ: P7: debug */
348 /* CMDQ sw tokens
367 /* Notify normal CMDQ there are some secure task done
368 * MUST NOT CHANGE, this token sync with secure world
372 /* CMDQ use sw token */
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
388 * MUST NOT CHANGE, these tokens sync with MDP
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/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_cmdq.c1 // SPDX-License-Identifier: GPL-2.0-only
78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
96 BUFDESC_LCMD_LEN = 2, /* 16 bytes - 2(8 byte unit) */
97 BUFDESC_SCMD_LEN = 3, /* 24 bytes - 3(8 byte unit) */
101 CTRL_SECT_LEN = 1, /* 4 bytes (ctrl) - 1(8 byte unit) */
102 CTRL_DIRECT_SECT_LEN = 2, /* 12 bytes (ctrl + rsvd) - 2(8 byte unit) */
120 * hinic_alloc_cmdq_buf - alloc buffer for sending command
124 * Return 0 - Success, negative - Failure
129 struct hinic_hwif *hwif = cmdqs->hwif; in hinic_alloc_cmdq_buf()
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2021-2021 Hisilicon Limited.
10 dma_addr_t dma = ring->desc_dma_addr; in hclge_comm_cmd_config_regs()
13 if (ring->ring_type == HCLGE_COMM_TYPE_CSQ) { in hclge_comm_cmd_config_regs()
20 reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S; in hclge_comm_cmd_config_regs()
29 reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S; in hclge_comm_cmd_config_regs()
38 hclge_comm_cmd_config_regs(hw, &hw->cmq.csq); in hclge_comm_cmd_init_regs()
39 hclge_comm_cmd_config_regs(hw, &hw->cmq.crq); in hclge_comm_cmd_init_regs()
44 desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR | in hclge_comm_cmd_reuse_desc()
47 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR); in hclge_comm_cmd_reuse_desc()
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/openbmc/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_rcfw.c2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
57 * bnxt_qplib_map_rc - map return type based on opcode
95 return -ETIMEDOUT; in bnxt_qplib_map_rc()
100 * bnxt_re_is_fw_stalled - Check firmware health
105 * rcfw->max_timeout, consider firmware as stalled.
109 * -ENODEV if firmware is not responding
114 struct bnxt_qplib_cmdq_ctx *cmdq; in bnxt_re_is_fw_stalled() local
117 crsqe = &rcfw->crsqe_tbl[cookie]; in bnxt_re_is_fw_stalled()
118 cmdq = &rcfw->cmdq; in bnxt_re_is_fw_stalled()
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/openbmc/linux/drivers/accel/ivpu/
H A Divpu_mmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
39 #define IVPU_MMU_Q_WRAP_MASK (IVPU_MMU_Q_WRAP_BIT - 1)
40 #define IVPU_MMU_Q_IDX_MASK (IVPU_MMU_Q_COUNT - 1)
189 #define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(VPU_37XX_HOST_MMU_GERROR, CMDQ)) | \
211 return "Transaction marks non-substream disabled"; in ivpu_mmu_event_to_str()
239 return "Unknown CMDQ command"; in ivpu_mmu_event_to_str()
279 struct ivpu_mmu_info *mmu = vdev->mmu; in ivpu_mmu_cdtab_alloc()
280 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; in ivpu_mmu_cdtab_alloc()
283 cdtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &cdtab->dma, GFP_KERNEL); in ivpu_mmu_cdtab_alloc()
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/openbmc/qemu/hw/arm/
H A Dsmmuv3.c2 * Copyright (C) 2014-2016 Broadcom Corporation
24 #include "hw/qdev-properties.h"
25 #include "hw/qdev-core.h"
30 #include "qemu/error-report.h"
34 #include "smmuv3-internal.h"
35 #include "smmu-internal.h"
38 (cfg)->record_faults) || \
40 (cfg)->s2cfg.record_faults))
43 * smmuv3_trigger_irq - pulse @irq if enabled and update
67 uint32_t pending = s->gerror ^ s->gerrorn; in smmuv3_trigger_irq()
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H A Dvirt.c2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
56 #include "qemu/error-report.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
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/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dtrans.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
[all …]
/openbmc/linux/drivers/scsi/aacraid/
H A Dcomminit.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
59 const unsigned long fibsize = dev->max_fib_size; in aac_alloc_comm()
66 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE1) || in aac_alloc_comm()
67 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2) || in aac_alloc_comm()
68 (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3 && in aac_alloc_comm()
69 !dev->sa_firmware)) { in aac_alloc_comm()
71 (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB) in aac_alloc_comm()
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H A Dcommsup.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
42 * fib_map_alloc - allocate the fib objects
51 if (dev->max_fib_size > AAC_MAX_NATIVE_SIZE) in fib_map_alloc()
52 dev->max_cmd_size = AAC_MAX_NATIVE_SIZE; in fib_map_alloc()
54 dev->max_cmd_size = dev->max_fib_size; in fib_map_alloc()
55 if (dev->max_fib_size < AAC_MAX_NATIVE_SIZE) { in fib_map_alloc()
56 dev->max_cmd_size = AAC_MAX_NATIVE_SIZE; in fib_map_alloc()
[all …]
H A Daacraid.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
34 /*------------------------------------------------------------------------------
36 *----------------------------------------------------------------------------*/
61 /* Bit definitions in IOA->Host Interrupt Register */
90 # define AAC_DRIVER_BRANCH "-custom"
95 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
106 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
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/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
44 * - checks DMA pointer
45 * - WREG, MSG_PROT are not allowed.
[all …]
/openbmc/linux/drivers/acpi/arm64/
H A Diort.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
69 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
76 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
78 * @node: IORT table node to be looked-up
[all …]
/openbmc/linux/drivers/scsi/
H A Dncr53c8xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** Device driver for the PCI-SCSI NCR538XX controller family.
8 **-----------------------------------------------------------------------------
22 ** Stefan Esser <se@mi.Uni-Koeln.de>
27 **-----------------------------------------------------------------------------
38 ** Support for Fast-20 scsi.
42 ** Support for Fast-40 scsi.
43 ** Support for on-Board RAM.
46 ** Full support for scsi scripts instructions pre-fetching.
57 ** Low PCI traffic for command handling when on-chip RAM is present.
[all …]
/openbmc/linux/drivers/staging/wlan-ng/
H A Dprism2sta.c1 // SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
7 * --------------------------------------------------------------------
9 * linux-wlan
11 * --------------------------------------------------------------------
13 * Inquiries regarding the linux-wlan Open Source project can be
17 * info@linux-wlan.com
18 * http://www.linux-wlan.com
20 * --------------------------------------------------------------------
25 * --------------------------------------------------------------------
30 * --------------------------------------------------------------------
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/
H A Dhns3_enet.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
54 static int debug = -1;
79 /* hns3_pci_tbl - PCI Device ID Table
387 napi_schedule_irqoff(&tqp_vector->napi); in hns3_irq_handle()
388 tqp_vector->event_cnt++; in hns3_irq_handle()
398 for (i = 0; i < priv->vector_num; i++) { in hns3_nic_uninit_irq()
399 tqp_vectors = &priv->tqp_vector[i]; in hns3_nic_uninit_irq()
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) in hns3_nic_uninit_irq()
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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