1*1b3418acSYongqiang Niu /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*1b3418acSYongqiang Niu /* 3*1b3418acSYongqiang Niu * Copyright (C) 2022 MediaTek Inc. 4*1b3418acSYongqiang Niu * Author: Yongqiang Niu <yongqiang.niu@mediatek.com> 5*1b3418acSYongqiang Niu */ 6*1b3418acSYongqiang Niu 7*1b3418acSYongqiang Niu #ifndef _DT_BINDINGS_GCE_MT8186_H 8*1b3418acSYongqiang Niu #define _DT_BINDINGS_GCE_MT8186_H 9*1b3418acSYongqiang Niu 10*1b3418acSYongqiang Niu /* assign timeout 0 also means default */ 11*1b3418acSYongqiang Niu #define CMDQ_NO_TIMEOUT 0xffffffff 12*1b3418acSYongqiang Niu #define CMDQ_TIMEOUT_DEFAULT 1000 13*1b3418acSYongqiang Niu 14*1b3418acSYongqiang Niu /* GCE thread priority */ 15*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_LOWEST 0 16*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_1 1 17*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_2 2 18*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_3 3 19*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_4 4 20*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_5 5 21*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_6 6 22*1b3418acSYongqiang Niu #define CMDQ_THR_PRIO_HIGHEST 7 23*1b3418acSYongqiang Niu 24*1b3418acSYongqiang Niu /* CPR count in 32bit register */ 25*1b3418acSYongqiang Niu #define GCE_CPR_COUNT 1312 26*1b3418acSYongqiang Niu 27*1b3418acSYongqiang Niu /* GCE subsys table */ 28*1b3418acSYongqiang Niu #define SUBSYS_1300XXXX 0 29*1b3418acSYongqiang Niu #define SUBSYS_1400XXXX 1 30*1b3418acSYongqiang Niu #define SUBSYS_1401XXXX 2 31*1b3418acSYongqiang Niu #define SUBSYS_1402XXXX 3 32*1b3418acSYongqiang Niu #define SUBSYS_1502XXXX 4 33*1b3418acSYongqiang Niu #define SUBSYS_1582XXXX 5 34*1b3418acSYongqiang Niu #define SUBSYS_1B00XXXX 6 35*1b3418acSYongqiang Niu #define SUBSYS_1C00XXXX 7 36*1b3418acSYongqiang Niu #define SUBSYS_1C10XXXX 8 37*1b3418acSYongqiang Niu #define SUBSYS_1000XXXX 9 38*1b3418acSYongqiang Niu #define SUBSYS_1001XXXX 10 39*1b3418acSYongqiang Niu #define SUBSYS_1020XXXX 11 40*1b3418acSYongqiang Niu #define SUBSYS_1021XXXX 12 41*1b3418acSYongqiang Niu #define SUBSYS_1022XXXX 13 42*1b3418acSYongqiang Niu #define SUBSYS_1023XXXX 14 43*1b3418acSYongqiang Niu #define SUBSYS_1060XXXX 15 44*1b3418acSYongqiang Niu #define SUBSYS_1602XXXX 16 45*1b3418acSYongqiang Niu #define SUBSYS_1608XXXX 17 46*1b3418acSYongqiang Niu #define SUBSYS_1700XXXX 18 47*1b3418acSYongqiang Niu #define SUBSYS_1701XXXX 19 48*1b3418acSYongqiang Niu #define SUBSYS_1702XXXX 20 49*1b3418acSYongqiang Niu #define SUBSYS_1703XXXX 21 50*1b3418acSYongqiang Niu #define SUBSYS_1706XXXX 22 51*1b3418acSYongqiang Niu #define SUBSYS_1A00XXXX 23 52*1b3418acSYongqiang Niu #define SUBSYS_1A01XXXX 24 53*1b3418acSYongqiang Niu #define SUBSYS_1A02XXXX 25 54*1b3418acSYongqiang Niu #define SUBSYS_1A03XXXX 26 55*1b3418acSYongqiang Niu #define SUBSYS_1A04XXXX 27 56*1b3418acSYongqiang Niu #define SUBSYS_1A05XXXX 28 57*1b3418acSYongqiang Niu #define SUBSYS_1A06XXXX 29 58*1b3418acSYongqiang Niu #define SUBSYS_NO_SUPPORT 99 59*1b3418acSYongqiang Niu 60*1b3418acSYongqiang Niu /* GCE General Purpose Register (GPR) support 61*1b3418acSYongqiang Niu * Leave note for scenario usage here 62*1b3418acSYongqiang Niu */ 63*1b3418acSYongqiang Niu /* GCE: write mask */ 64*1b3418acSYongqiang Niu #define GCE_GPR_R00 0x00 65*1b3418acSYongqiang Niu #define GCE_GPR_R01 0x01 66*1b3418acSYongqiang Niu /* MDP: P1: JPEG dest */ 67*1b3418acSYongqiang Niu #define GCE_GPR_R02 0x02 68*1b3418acSYongqiang Niu #define GCE_GPR_R03 0x03 69*1b3418acSYongqiang Niu /* MDP: PQ color */ 70*1b3418acSYongqiang Niu #define GCE_GPR_R04 0x04 71*1b3418acSYongqiang Niu /* MDP: 2D sharpness */ 72*1b3418acSYongqiang Niu #define GCE_GPR_R05 0x05 73*1b3418acSYongqiang Niu /* DISP: poll esd */ 74*1b3418acSYongqiang Niu #define GCE_GPR_R06 0x06 75*1b3418acSYongqiang Niu #define GCE_GPR_R07 0x07 76*1b3418acSYongqiang Niu /* MDP: P4: 2D sharpness dst */ 77*1b3418acSYongqiang Niu #define GCE_GPR_R08 0x08 78*1b3418acSYongqiang Niu #define GCE_GPR_R09 0x09 79*1b3418acSYongqiang Niu /* VCU: poll with timeout for GPR timer */ 80*1b3418acSYongqiang Niu #define GCE_GPR_R10 0x0A 81*1b3418acSYongqiang Niu #define GCE_GPR_R11 0x0B 82*1b3418acSYongqiang Niu /* CMDQ: debug */ 83*1b3418acSYongqiang Niu #define GCE_GPR_R12 0x0C 84*1b3418acSYongqiang Niu #define GCE_GPR_R13 0x0D 85*1b3418acSYongqiang Niu /* CMDQ: P7: debug */ 86*1b3418acSYongqiang Niu #define GCE_GPR_R14 0x0E 87*1b3418acSYongqiang Niu #define GCE_GPR_R15 0x0F 88*1b3418acSYongqiang Niu 89*1b3418acSYongqiang Niu /* GCE hardware events */ 90*1b3418acSYongqiang Niu /* VDEC */ 91*1b3418acSYongqiang Niu #define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0 92*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_INT 1 93*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_PAUSE 2 94*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_DEC_ERROR 3 95*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDEC_TIMEOUT 4 96*1b3418acSYongqiang Niu #define CMDQ_EVENT_DRAM_ACCESS_DONE 5 97*1b3418acSYongqiang Niu #define CMDQ_EVENT_INI_FETCH_RDY 6 98*1b3418acSYongqiang Niu #define CMDQ_EVENT_PROCESS_FLAG 7 99*1b3418acSYongqiang Niu #define CMDQ_EVENT_SEARCH_START_CODE_DONE 8 100*1b3418acSYongqiang Niu #define CMDQ_EVENT_REF_REORDER_DONE 9 101*1b3418acSYongqiang Niu #define CMDQ_EVENT_WP_TBLE_DONE 10 102*1b3418acSYongqiang Niu #define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11 103*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15 104*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16 105*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17 106*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18 107*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19 108*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20 109*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21 110*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22 111*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23 112*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24 113*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25 114*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26 115*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27 116*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28 117*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29 118*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30 119*1b3418acSYongqiang Niu #define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31 120*1b3418acSYongqiang Niu #define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32 121*1b3418acSYongqiang Niu 122*1b3418acSYongqiang Niu /* CAM */ 123*1b3418acSYongqiang Niu #define CMDQ_EVENT_ISP_FRAME_DONE_A 65 124*1b3418acSYongqiang Niu #define CMDQ_EVENT_ISP_FRAME_DONE_B 66 125*1b3418acSYongqiang Niu #define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 126*1b3418acSYongqiang Niu #define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 127*1b3418acSYongqiang Niu #define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 128*1b3418acSYongqiang Niu #define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 129*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 130*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 131*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 132*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 133*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 134*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 135*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 136*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 137*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 138*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 139*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 140*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 141*1b3418acSYongqiang Niu #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 142*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_OVRUN_A_INT 88 143*1b3418acSYongqiang Niu #define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 144*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_OVRUN_B_INT 90 145*1b3418acSYongqiang Niu #define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 146*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_OVRUN_M0_INT 94 147*1b3418acSYongqiang Niu #define CMDQ_EVENT_R1_ERROR_M0_INT 95 148*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_GRABERR_M0_INT 96 149*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_GRABERR_A_INT 98 150*1b3418acSYongqiang Niu #define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 151*1b3418acSYongqiang Niu #define CMDQ_EVENT_TG_GRABERR_B_INT 100 152*1b3418acSYongqiang Niu #define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 153*1b3418acSYongqiang Niu /* VENC */ 154*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 155*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 156*1b3418acSYongqiang Niu #define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 157*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 158*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 159*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 160*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 161*1b3418acSYongqiang Niu #define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 162*1b3418acSYongqiang Niu /* IPE */ 163*1b3418acSYongqiang Niu #define CMDQ_EVENT_FDVT_DONE 161 164*1b3418acSYongqiang Niu #define CMDQ_EVENT_FE_DONE 162 165*1b3418acSYongqiang Niu #define CMDQ_EVENT_RSC_DONE 163 166*1b3418acSYongqiang Niu #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164 167*1b3418acSYongqiang Niu #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165 168*1b3418acSYongqiang Niu /* IMG2 */ 169*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT0 193 170*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT1 194 171*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT2 195 172*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT3 196 173*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT4 197 174*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT5 198 175*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT6 199 176*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT7 200 177*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT8 201 178*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT9 202 179*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT10 203 180*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT11 204 181*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT12 205 182*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT13 206 183*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT14 207 184*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT15 208 185*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT16 209 186*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT17 210 187*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT18 211 188*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT19 212 189*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT20 213 190*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT21 214 191*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT22 215 192*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG2_EVENT23 216 193*1b3418acSYongqiang Niu /* IMG1 */ 194*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT0 225 195*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT1 226 196*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT2 227 197*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT3 228 198*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT4 229 199*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT5 230 200*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT6 231 201*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT7 232 202*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT8 233 203*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT9 234 204*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT10 235 205*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT11 236 206*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT12 237 207*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT13 238 208*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT14 239 209*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT15 240 210*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT16 241 211*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT17 242 212*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT18 243 213*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT19 244 214*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT20 245 215*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT21 246 216*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT22 247 217*1b3418acSYongqiang Niu #define CMDQ_EVENT_GCE_IMG1_EVENT23 248 218*1b3418acSYongqiang Niu /* MDP */ 219*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA0_SOF 256 220*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA1_SOF 257 221*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL0_SOF 258 222*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL1_SOF 259 223*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_HDR0_SOF 260 224*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ0_SOF 261 225*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ1_SOF 262 226*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT0_SOF 263 227*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT1_SOF 264 228*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP0_SOF 265 229*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP1_SOF 266 230*1b3418acSYongqiang Niu #define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267 231*1b3418acSYongqiang Niu #define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268 232*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_COLOR0_SOF 269 233*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288 234*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289 235*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 236*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 237*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292 238*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293 239*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 240*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 241*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296 242*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297 243*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298 244*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299 245*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300 246*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301 247*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302 248*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303 249*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304 250*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305 251*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306 252*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307 253*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308 254*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309 255*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310 256*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 257*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 258*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 259*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 260*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 261*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 262*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 263*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 264*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 265*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 266*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 267*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 268*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 269*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 270*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 271*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 272*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336 273*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337 274*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 275*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 276*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340 277*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341 278*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 279*1b3418acSYongqiang Niu #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 280*1b3418acSYongqiang Niu /* DISP */ 281*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_SOF 384 282*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 283*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_RDMA0_SOF 386 284*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_RSZ0_SOF 387 285*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_COLOR0_SOF 388 286*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CCORR0_SOF 389 287*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CCORR1_SOF 390 288*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_AAL0_SOF 391 289*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_GAMMA0_SOF 392 290*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_POSTMASK0_SOF 393 291*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_DITHER0_SOF 394 292*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CM0_SOF 395 293*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_SPR0_SOF 396 294*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397 295*1b3418acSYongqiang Niu #define CMDQ_EVENT_DSI0_SOF 398 296*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_WDMA0_SOF 399 297*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_PWM0_SOF 400 298*1b3418acSYongqiang Niu #define CMDQ_EVENT_DSI0_FRAME_DONE 410 299*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411 300*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412 301*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413 302*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414 303*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415 304*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416 305*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417 306*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418 307*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420 308*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421 309*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422 310*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423 311*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424 312*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425 313*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426 314*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 315*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 316*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 317*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 318*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 319*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 320*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 321*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 322*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 323*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 324*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 325*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 326*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 327*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 328*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 329*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 330*1b3418acSYongqiang Niu #define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 331*1b3418acSYongqiang Niu #define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 332*1b3418acSYongqiang Niu #define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 333*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 334*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 335*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 336*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456 337*1b3418acSYongqiang Niu #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457 338*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458 339*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459 340*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460 341*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461 342*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462 343*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463 344*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464 345*1b3418acSYongqiang Niu #define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465 346*1b3418acSYongqiang Niu #define CMDQ_EVENT_OUT_EVENT_0 898 347*1b3418acSYongqiang Niu 348*1b3418acSYongqiang Niu /* CMDQ sw tokens 349*1b3418acSYongqiang Niu * Following definitions are gce sw token which may use by clients 350*1b3418acSYongqiang Niu * event operation API. 351*1b3418acSYongqiang Niu * Note that token 512 to 639 may set secure 352*1b3418acSYongqiang Niu */ 353*1b3418acSYongqiang Niu 354*1b3418acSYongqiang Niu /* end of hw event and begin of sw token */ 355*1b3418acSYongqiang Niu #define CMDQ_MAX_HW_EVENT 512 356*1b3418acSYongqiang Niu 357*1b3418acSYongqiang Niu /* Config thread notify trigger thread */ 358*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 359*1b3418acSYongqiang Niu /* Trigger thread notify config thread */ 360*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_STREAM_EOF 641 361*1b3418acSYongqiang Niu /* Block Trigger thread until the ESD check finishes. */ 362*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_ESD_EOF 642 363*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 364*1b3418acSYongqiang Niu /* check CABC setup finish */ 365*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_CABC_EOF 644 366*1b3418acSYongqiang Niu 367*1b3418acSYongqiang Niu /* Notify normal CMDQ there are some secure task done 368*1b3418acSYongqiang Niu * MUST NOT CHANGE, this token sync with secure world 369*1b3418acSYongqiang Niu */ 370*1b3418acSYongqiang Niu #define CMDQ_SYNC_SECURE_THR_EOF 647 371*1b3418acSYongqiang Niu 372*1b3418acSYongqiang Niu /* CMDQ use sw token */ 373*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_USER_0 649 374*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_USER_1 650 375*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 376*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_TPR_LOCK 652 377*1b3418acSYongqiang Niu 378*1b3418acSYongqiang Niu /* ISP sw token */ 379*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_MSS 665 380*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_MSF 666 381*1b3418acSYongqiang Niu 382*1b3418acSYongqiang Niu /* DISP sw token */ 383*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_SODI 671 384*1b3418acSYongqiang Niu 385*1b3418acSYongqiang Niu /* GPR access tokens (for register backup) 386*1b3418acSYongqiang Niu * There are 15 32-bit GPR, 3 GPR form a set 387*1b3418acSYongqiang Niu * (64-bit for address, 32-bit for value) 388*1b3418acSYongqiang Niu * MUST NOT CHANGE, these tokens sync with MDP 389*1b3418acSYongqiang Niu */ 390*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_GPR_SET_0 700 391*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_GPR_SET_1 701 392*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_GPR_SET_2 702 393*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_GPR_SET_3 703 394*1b3418acSYongqiang Niu #define CMDQ_SYNC_TOKEN_GPR_SET_4 704 395*1b3418acSYongqiang Niu 396*1b3418acSYongqiang Niu /* Resource lock event to control resource in GCE thread */ 397*1b3418acSYongqiang Niu #define CMDQ_SYNC_RESOURCE_WROT0 710 398*1b3418acSYongqiang Niu #define CMDQ_SYNC_RESOURCE_WROT1 711 399*1b3418acSYongqiang Niu 400*1b3418acSYongqiang Niu /* event for gpr timer, used in sleep and poll with timeout */ 401*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R0 994 402*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R1 995 403*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R2 996 404*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R3 997 405*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R4 998 406*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R5 999 407*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R6 1000 408*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R7 1001 409*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R8 1002 410*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R9 1003 411*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R10 1004 412*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R11 1005 413*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R12 1006 414*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R13 1007 415*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R14 1008 416*1b3418acSYongqiang Niu #define CMDQ_TOKEN_GPR_TIMER_R15 1009 417*1b3418acSYongqiang Niu 418*1b3418acSYongqiang Niu #define CMDQ_EVENT_MAX 0x3FF 419*1b3418acSYongqiang Niu /* CMDQ sw tokens END */ 420*1b3418acSYongqiang Niu 421*1b3418acSYongqiang Niu #endif 422